Testing Superconductor Logic Integrated Circuits

A.J. Arun, Hans G. Kerkhoff

    Research output: Contribution to conferencePaper

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    Abstract

    Superconductor logic has the potential of extremely low-power consumption and ultra-fast digital signal processing. Unfortunately, the obtained yield of the present processes is low and specific faults occur. This paper deals with fault-modelling, Design-for-Test structures, and ATPG for these integrated circuits.
    Original languageUndefined
    Pages239-244
    Number of pages6
    Publication statusPublished - 22 May 2005
    Event10th IEEE European Test Symposium, ETS 2005 - Tallinn, Estonia
    Duration: 22 May 200525 May 2005
    Conference number: 10

    Conference

    Conference10th IEEE European Test Symposium, ETS 2005
    Abbreviated titleETS
    CountryEstonia
    CityTallinn
    Period22/05/0525/05/05

    Keywords

    • Design-for-Test
    • Defect Monitor Structures
    • Fault modelling
    • ATPG
    • IR-76672
    • EWI-19979

    Cite this

    Arun, A. J., & Kerkhoff, H. G. (2005). Testing Superconductor Logic Integrated Circuits. 239-244. Paper presented at 10th IEEE European Test Symposium, ETS 2005, Tallinn, Estonia.