Testing Superconductor Logic Integrated Circuits

A.J. Arun, Hans G. Kerkhoff

Research output: Contribution to conferencePaperAcademicpeer-review

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Abstract

Superconductor logic has the potential of extremely low-power consumption and ultra-fast digital signal processing. Unfortunately, the obtained yield of the present processes is low and specific faults occur. This paper deals with fault-modelling, Design-for-Test structures, and ATPG for these integrated circuits.
Original languageUndefined
Pages239-244
Number of pages6
Publication statusPublished - 22 May 2005
Event10th IEEE European Test Symposium, ETS 2005 - Tallinn, Estonia
Duration: 22 May 200525 May 2005
Conference number: 10

Conference

Conference10th IEEE European Test Symposium, ETS 2005
Abbreviated titleETS
CountryEstonia
CityTallinn
Period22/05/0525/05/05

Keywords

  • Design-for-Test
  • Defect Monitor Structures
  • Fault modelling
  • ATPG
  • IR-76672
  • EWI-19979

Cite this

Arun, A. J., & Kerkhoff, H. G. (2005). Testing Superconductor Logic Integrated Circuits. 239-244. Paper presented at 10th IEEE European Test Symposium, ETS 2005, Tallinn, Estonia.
Arun, A.J. ; Kerkhoff, Hans G. / Testing Superconductor Logic Integrated Circuits. Paper presented at 10th IEEE European Test Symposium, ETS 2005, Tallinn, Estonia.6 p.
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Arun, AJ & Kerkhoff, HG 2005, 'Testing Superconductor Logic Integrated Circuits' Paper presented at 10th IEEE European Test Symposium, ETS 2005, Tallinn, Estonia, 22/05/05 - 25/05/05, pp. 239-244.

Testing Superconductor Logic Integrated Circuits. / Arun, A.J.; Kerkhoff, Hans G.

2005. 239-244 Paper presented at 10th IEEE European Test Symposium, ETS 2005, Tallinn, Estonia.

Research output: Contribution to conferencePaperAcademicpeer-review

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AB - Superconductor logic has the potential of extremely low-power consumption and ultra-fast digital signal processing. Unfortunately, the obtained yield of the present processes is low and specific faults occur. This paper deals with fault-modelling, Design-for-Test structures, and ATPG for these integrated circuits.

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KW - Defect Monitor Structures

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KW - ATPG

KW - IR-76672

KW - EWI-19979

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Arun AJ, Kerkhoff HG. Testing Superconductor Logic Integrated Circuits. 2005. Paper presented at 10th IEEE European Test Symposium, ETS 2005, Tallinn, Estonia.