Testing Superconductor Logic Integrated Circuits

A.J. Arun; Hans G. Kerkhoff

Testing Superconductor Logic Integrated Circuits

A.J. Arun
, Hans G. Kerkhoff

Research output: Contribution to conference › Paper › peer-review

219 Downloads (Pure)

Abstract

Superconductor logic has the potential of extremely low-power consumption and ultra-fast digital signal processing. Unfortunately, the obtained yield of the present processes is low and specific faults occur. This paper deals with fault-modelling, Design-for-Test structures, and ATPG for these integrated circuits.

Original language	Undefined
Pages	239-244
Number of pages	6
Publication status	Published - 22 May 2005
Event	10th IEEE European Test Symposium, ETS 2005 - Tallinn, Estonia Duration: 22 May 2005 → 25 May 2005 Conference number: 10

Conference

Conference	10th IEEE European Test Symposium, ETS 2005
Abbreviated title	ETS
Country/Territory	Estonia
City	Tallinn
Period	22/05/05 → 25/05/05

Keywords

Design-for-Test
Defect Monitor Structures
Fault modelling
ATPG
IR-76672
EWI-19979

Access to Document

http://ati.ttu.ee/ETS/index.php?page=41

Cite this

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title = "Testing Superconductor Logic Integrated Circuits",

abstract = "Superconductor logic has the potential of extremely low-power consumption and ultra-fast digital signal processing. Unfortunately, the obtained yield of the present processes is low and specific faults occur. This paper deals with fault-modelling, Design-for-Test structures, and ATPG for these integrated circuits.",

keywords = "Design-for-Test, Defect Monitor Structures, Fault modelling, ATPG, IR-76672, EWI-19979",

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AU - Kerkhoff, Hans G.

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N2 - Superconductor logic has the potential of extremely low-power consumption and ultra-fast digital signal processing. Unfortunately, the obtained yield of the present processes is low and specific faults occur. This paper deals with fault-modelling, Design-for-Test structures, and ATPG for these integrated circuits.

AB - Superconductor logic has the potential of extremely low-power consumption and ultra-fast digital signal processing. Unfortunately, the obtained yield of the present processes is low and specific faults occur. This paper deals with fault-modelling, Design-for-Test structures, and ATPG for these integrated circuits.

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KW - Defect Monitor Structures

KW - Fault modelling

KW - ATPG

KW - IR-76672

KW - EWI-19979

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T2 - 10th IEEE European Test Symposium, ETS 2005

Y2 - 22 May 2005 through 25 May 2005

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