The Chameleon Architecture for Streaming DSP Applications

N. Bergmann (Editor), Gerardus Johannes Maria Smit, Andre B.J. Kokkeler, P.T. Wolkotte, P.K.F. Holzenspies, M.D. van de Burgwal, P.M. Heysters

    Research output: Contribution to journalArticleAcademicpeer-review

    16 Citations (Scopus)
    57 Downloads (Pure)

    Abstract

    We focus on architectures for streaming DSP applications such as wireless baseband processing and image processing. We aim at a single generic architecture that is capable of dealing with different DSP applications. This architecture has to be energy efficient and fault tolerant. We introduce a heterogeneous tiled architecture and present the details of a domain-specific reconfigurable tile processor called Montium. This reconfigurable processor has a small footprint (1.8 mm$^2$ in a 130 nm process), is power efficient and exploits the locality of reference principle. Reconfiguring the device is very fast, for example, loading the coefficients for a 200 tap FIR filter is done within 80 clock cycles. The tiles on the tiled architecture are connected to a Network-on-Chip (NoC) via a network interface (NI). Two NoCs have been developed: a packet-switched and a circuit-switched version. Both provide two types of services: guaranteed throughput (GT) and best effort (BE). For both NoCs estimates of power consumption are presented. The NI synchronizes data transfers, configures and starts/stops the tile processor. For dynamically mapping applications onto the tiled architecture, we introduce a run-time mapping tool.
    Original languageEnglish
    Pages (from-to)78082
    Number of pages10
    JournalEURASIP journal on embedded systems
    Volume2007
    Issue numberP2773
    DOIs
    Publication statusPublished - 2007

    Fingerprint

    Tile
    Interfaces (computer)
    FIR filters
    Data transfer
    Clocks
    Image processing
    Electric power utilization
    Throughput
    Networks (circuits)
    Processing

    Keywords

    • IR-67115
    • EWI-9856
    • EC Grant Agreement nr.: FP6/001908
    • CAES-EEA: Efficient Embedded Architectures
    • METIS-242171

    Cite this

    Bergmann, N. (Ed.), Smit, G. J. M., Kokkeler, A. B. J., Wolkotte, P. T., Holzenspies, P. K. F., van de Burgwal, M. D., & Heysters, P. M. (2007). The Chameleon Architecture for Streaming DSP Applications. EURASIP journal on embedded systems, 2007(P2773), 78082. https://doi.org/10.1155/2007/78082
    Bergmann, N. (Editor) ; Smit, Gerardus Johannes Maria ; Kokkeler, Andre B.J. ; Wolkotte, P.T. ; Holzenspies, P.K.F. ; van de Burgwal, M.D. ; Heysters, P.M. / The Chameleon Architecture for Streaming DSP Applications. In: EURASIP journal on embedded systems. 2007 ; Vol. 2007, No. P2773. pp. 78082.
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    Bergmann, N (ed.), Smit, GJM, Kokkeler, ABJ, Wolkotte, PT, Holzenspies, PKF, van de Burgwal, MD & Heysters, PM 2007, 'The Chameleon Architecture for Streaming DSP Applications', EURASIP journal on embedded systems, vol. 2007, no. P2773, pp. 78082. https://doi.org/10.1155/2007/78082

    The Chameleon Architecture for Streaming DSP Applications. / Bergmann, N. (Editor); Smit, Gerardus Johannes Maria; Kokkeler, Andre B.J.; Wolkotte, P.T.; Holzenspies, P.K.F.; van de Burgwal, M.D.; Heysters, P.M.

    In: EURASIP journal on embedded systems, Vol. 2007, No. P2773, 2007, p. 78082.

    Research output: Contribution to journalArticleAcademicpeer-review

    TY - JOUR

    T1 - The Chameleon Architecture for Streaming DSP Applications

    AU - Smit, Gerardus Johannes Maria

    AU - Kokkeler, Andre B.J.

    AU - Wolkotte, P.T.

    AU - Holzenspies, P.K.F.

    AU - van de Burgwal, M.D.

    AU - Heysters, P.M.

    A2 - Bergmann, N.

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    N2 - We focus on architectures for streaming DSP applications such as wireless baseband processing and image processing. We aim at a single generic architecture that is capable of dealing with different DSP applications. This architecture has to be energy efficient and fault tolerant. We introduce a heterogeneous tiled architecture and present the details of a domain-specific reconfigurable tile processor called Montium. This reconfigurable processor has a small footprint (1.8 mm$^2$ in a 130 nm process), is power efficient and exploits the locality of reference principle. Reconfiguring the device is very fast, for example, loading the coefficients for a 200 tap FIR filter is done within 80 clock cycles. The tiles on the tiled architecture are connected to a Network-on-Chip (NoC) via a network interface (NI). Two NoCs have been developed: a packet-switched and a circuit-switched version. Both provide two types of services: guaranteed throughput (GT) and best effort (BE). For both NoCs estimates of power consumption are presented. The NI synchronizes data transfers, configures and starts/stops the tile processor. For dynamically mapping applications onto the tiled architecture, we introduce a run-time mapping tool.

    AB - We focus on architectures for streaming DSP applications such as wireless baseband processing and image processing. We aim at a single generic architecture that is capable of dealing with different DSP applications. This architecture has to be energy efficient and fault tolerant. We introduce a heterogeneous tiled architecture and present the details of a domain-specific reconfigurable tile processor called Montium. This reconfigurable processor has a small footprint (1.8 mm$^2$ in a 130 nm process), is power efficient and exploits the locality of reference principle. Reconfiguring the device is very fast, for example, loading the coefficients for a 200 tap FIR filter is done within 80 clock cycles. The tiles on the tiled architecture are connected to a Network-on-Chip (NoC) via a network interface (NI). Two NoCs have been developed: a packet-switched and a circuit-switched version. Both provide two types of services: guaranteed throughput (GT) and best effort (BE). For both NoCs estimates of power consumption are presented. The NI synchronizes data transfers, configures and starts/stops the tile processor. For dynamically mapping applications onto the tiled architecture, we introduce a run-time mapping tool.

    KW - IR-67115

    KW - EWI-9856

    KW - EC Grant Agreement nr.: FP6/001908

    KW - CAES-EEA: Efficient Embedded Architectures

    KW - METIS-242171

    U2 - 10.1155/2007/78082

    DO - 10.1155/2007/78082

    M3 - Article

    VL - 2007

    SP - 78082

    JO - EURASIP journal on embedded systems

    JF - EURASIP journal on embedded systems

    SN - 1687-3955

    IS - P2773

    ER -

    Bergmann N, (ed.), Smit GJM, Kokkeler ABJ, Wolkotte PT, Holzenspies PKF, van de Burgwal MD et al. The Chameleon Architecture for Streaming DSP Applications. EURASIP journal on embedded systems. 2007;2007(P2773):78082. https://doi.org/10.1155/2007/78082