The Chameleon Architecture for Streaming DSP Applications

N. Bergmann (Editor), Gerardus Johannes Maria Smit, Andre B.J. Kokkeler, P.T. Wolkotte, P.K.F. Holzenspies, M.D. van de Burgwal, P.M. Heysters

    Research output: Contribution to journalArticleAcademicpeer-review

    16 Citations (Scopus)
    99 Downloads (Pure)

    Abstract

    We focus on architectures for streaming DSP applications such as wireless baseband processing and image processing. We aim at a single generic architecture that is capable of dealing with different DSP applications. This architecture has to be energy efficient and fault tolerant. We introduce a heterogeneous tiled architecture and present the details of a domain-specific reconfigurable tile processor called Montium. This reconfigurable processor has a small footprint (1.8 mm$^2$ in a 130 nm process), is power efficient and exploits the locality of reference principle. Reconfiguring the device is very fast, for example, loading the coefficients for a 200 tap FIR filter is done within 80 clock cycles. The tiles on the tiled architecture are connected to a Network-on-Chip (NoC) via a network interface (NI). Two NoCs have been developed: a packet-switched and a circuit-switched version. Both provide two types of services: guaranteed throughput (GT) and best effort (BE). For both NoCs estimates of power consumption are presented. The NI synchronizes data transfers, configures and starts/stops the tile processor. For dynamically mapping applications onto the tiled architecture, we introduce a run-time mapping tool.
    Original languageEnglish
    Pages (from-to)78082
    Number of pages10
    JournalEURASIP journal on embedded systems
    Volume2007
    Issue numberP2773
    DOIs
    Publication statusPublished - 2007

    Keywords

    • IR-67115
    • EWI-9856
    • EC Grant Agreement nr.: FP6/001908
    • CAES-EEA: Efficient Embedded Architectures
    • METIS-242171

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