The Detection of Defects in a Niobium Tri-layer Process

A. Joseph Arun, Sander Heuvelmans, Gerrit J. Gerritsma, Hans G. Kerkhoff

Research output: Contribution to journalConference articleAcademicpeer-review

4 Citations (Scopus)
37 Downloads (Pure)

Abstract

Niobium (Nb) LTS processes are emerging as the technology for future ultra high-speed systems especially in the digital domain. As the number of Josephson Junctions (JJ) per chip has recently increased to around 90000, the quality of the process has to be assured so as to realize these complex circuits. Until now, very little or no information is available in the literature on how to achieve this. In this paper we present an approach and results of a study conducted on an RSFQ process. Measurements and SEM inspection were carried out on sample chips and a list of possible defects has been identified and described in detail. We have also developed test-structures for detection of the top-ranking defects, which will be used for yield analysis and the determination of the probability distribution of faults in the process. A test chip has been designed, based on the results of this study, and certain types of defects were introduced in the design to study the behavior of faulty junctions and interconnections.
Original languageEnglish
Pages (from-to)95-98
Number of pages4
JournalIEEE transactions on applied superconductivity
Volume13
Issue number2
DOIs
Publication statusPublished - 2003
Event2002 Applied Superconductivity Conference, ASC 2002 - Houston, United States
Duration: 4 Aug 20029 Aug 2002

Fingerprint

Niobium
niobium
chips
Defects
defects
ranking
Josephson junctions
lists
Probability distributions
inspection
emerging
Inspection
high speed
Scanning electron microscopy
scanning electron microscopy
Networks (circuits)

Keywords

  • METIS-207854
  • IR-43945
  • Defect-based testing
  • RSFQ circuit testing
  • PDM
  • Superconductor devices
  • Structural testing

Cite this

Arun, A. Joseph ; Heuvelmans, Sander ; Gerritsma, Gerrit J. ; Kerkhoff, Hans G. / The Detection of Defects in a Niobium Tri-layer Process. In: IEEE transactions on applied superconductivity. 2003 ; Vol. 13, No. 2. pp. 95-98.
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The Detection of Defects in a Niobium Tri-layer Process. / Arun, A. Joseph; Heuvelmans, Sander; Gerritsma, Gerrit J.; Kerkhoff, Hans G.

In: IEEE transactions on applied superconductivity, Vol. 13, No. 2, 2003, p. 95-98.

Research output: Contribution to journalConference articleAcademicpeer-review

TY - JOUR

T1 - The Detection of Defects in a Niobium Tri-layer Process

AU - Arun, A. Joseph

AU - Heuvelmans, Sander

AU - Gerritsma, Gerrit J.

AU - Kerkhoff, Hans G.

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N2 - Niobium (Nb) LTS processes are emerging as the technology for future ultra high-speed systems especially in the digital domain. As the number of Josephson Junctions (JJ) per chip has recently increased to around 90000, the quality of the process has to be assured so as to realize these complex circuits. Until now, very little or no information is available in the literature on how to achieve this. In this paper we present an approach and results of a study conducted on an RSFQ process. Measurements and SEM inspection were carried out on sample chips and a list of possible defects has been identified and described in detail. We have also developed test-structures for detection of the top-ranking defects, which will be used for yield analysis and the determination of the probability distribution of faults in the process. A test chip has been designed, based on the results of this study, and certain types of defects were introduced in the design to study the behavior of faulty junctions and interconnections.

AB - Niobium (Nb) LTS processes are emerging as the technology for future ultra high-speed systems especially in the digital domain. As the number of Josephson Junctions (JJ) per chip has recently increased to around 90000, the quality of the process has to be assured so as to realize these complex circuits. Until now, very little or no information is available in the literature on how to achieve this. In this paper we present an approach and results of a study conducted on an RSFQ process. Measurements and SEM inspection were carried out on sample chips and a list of possible defects has been identified and described in detail. We have also developed test-structures for detection of the top-ranking defects, which will be used for yield analysis and the determination of the probability distribution of faults in the process. A test chip has been designed, based on the results of this study, and certain types of defects were introduced in the design to study the behavior of faulty junctions and interconnections.

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KW - Defect-based testing

KW - RSFQ circuit testing

KW - PDM

KW - Superconductor devices

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