In this paper we present a systematic study on the effect of process and layout variation for grounded-gate NMOSTs and L VTSCRs in a 0.18μ,m technology under negative non-socketed Charged Device Model (CDM) stress. Failure Analysis of the stressed devices was done using Scanning Electron Microscopy (SEM). A comparison of the CDM test results with those of ggNMOSTs in various other technologies is also presented. It is shown that the CDM robustness of ggNMOSTs increases with technology scaling and that the performance ofL VTSCRs can be as good as that of ggNMOSTs under CDM stresses.
|Number of pages||6|
|Publication status||Published - 2002|
|Event||13th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, ESREF 2002 - Bellaria, Italy|
Duration: 7 Oct 2002 → 11 Oct 2002
Conference number: 13
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