The safe operating volume as a general measure for the operating limits of LDMOS transistors

A. Ferrara, P.G. Steeneken, A. Heringa, B.K. Boksteen, M. Swanenberg, A.J. Scholten, L. van Dijk, Jurriaan Schmitz, Raymond Josephus Engelbart Hueting

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    The operating limits of a transistor are conventionally determined by characterization of the curves that form the boundary of the safe operating area (SOA) in the twodimensional drain current-voltage (Id, Vds) plane [1, 2]. The shape of these SOA curves depends on parameters such as pulse time tpulse, ambient temperature Tamb and area of the transistor A [3, 4]. Consequently, this way of characterizing the safe operating limits does not result in a single safe operating range for the transistor, but in many different curves that depend on operating conditions and transistor geometry. Besides the drain-source voltage Vds and the gate-width Wgate normalized drain current Idn (Idn = Id/Wgate), the junction temperature Tj also plays an essential role in determining the safe operating limits of a transistor with a certain cross-section. Therefore, it is proposed to extend the SOA concept by adding a temperature Tj-axis. In this way, the safe operating range can be represented by a volume in the three dimensional (Idn, Vds, Tj) space, which we define as the safe operating volume (SOV). In this work, extensive measurements of the safe operating limits of SOI LDMOS transistors are presented. Integrated temperature sensors are used to measure the junction temperature of the devices up to the edge of the operating range. By comparing measured SOV data for varying tpulse, Tamb and A for devices of identical cross-section (Figs. 2- 5) it is demonstrated that the SOV is nearly independent of operating conditions and device area. This establishes the SOV as a general measure for the safe operating limits of transistors. The usefulness of the SOV concept is demonstrated by showing how conventional two-dimensional SOA curves for different operating conditions and device areas can be predicted once the SOV and the effective thermal impedance Zth,eff of the LDMOS transistor have been determined (Table I and Figs. 6-7).
    Original languageUndefined
    Title of host publicationInternational Electron Devices Meeting (IEDM 2013)
    Place of PublicationUSA
    PublisherIEEE Electron Devices Society
    Number of pages4
    ISBN (Print)978-1-4799-2306-9
    Publication statusPublished - 9 Dec 2013
    Event2013 IEEE International Electron Devices Meeting, IEDM 2013 - Washington Hilton, Washington, United States
    Duration: 9 Dec 201311 Dec 2013

    Publication series

    PublisherIEEE Electron Devices Society


    Conference2013 IEEE International Electron Devices Meeting, IEDM 2013
    Abbreviated titleIEDM 2013
    CountryUnited States


    • JunctionsLogic gatesSemiconductor device measurementSemiconductor optical amplifiersTemperature measurementTemperature sensorsTransistors
    • EWI-24309
    • Logic gates
    • Transistors
    • Semiconductor device measurement
    • Semiconductor optical amplifiers
    • Junctions
    • Temperature measurement
    • Temperature sensors
    • IR-89440
    • METIS-302643

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