The Synthesis of a Hardware Scheduler for Non-Manifest Loops

O. Mansour; Egbert Molenkamp; Th. Krol

doi:10.1109/DSD.2002.1115354

The Synthesis of a Hardware Scheduler for Non-Manifest Loops

O. Mansour, Egbert Molenkamp, Th. Krol

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

This paper addresses the hardware implementation of a dynamic scheduler for non-manifest data dependent periodic loops. Static scheduling techniques which are known to give near optimal scheduling-solutions for manifest loops, fail at scheduling non-manifest loops, since they lack the run time information needed which makes a static schedule feasible. In this paper a dynamic scheduling approach was chosen to circumvent this problem. We present a case study using VHDL were the focus lies on implementations with minimal memory usage and low communication overhead between various components of the architecture. This has resulted in an efficient and synthesisable system.

Original language	Undefined
Title of host publication	Euromicro Symposium on Digital System Design (DSD'02)
Publisher	IEEE
Pages	78-85
Number of pages	8
ISBN (Print)	0-7695-1790-0
DOIs	https://doi.org/10.1109/DSD.2002.1115354
Publication status	Published - Sep 2002
Event	5th EUROMICRO Symposium on Digital System Design, DSD 2002 - Dortmund, Germany Duration: 4 Sep 2002 → 6 Sep 2002 Conference number: 5

Publication series

Name
Publisher	IEEE

Conference

Conference	5th EUROMICRO Symposium on Digital System Design, DSD 2002
Abbreviated title	DSD
Country/Territory	Germany
City	Dortmund
Period	4/09/02 → 6/09/02

Keywords

METIS-209133
CAES-EEA: Efficient Embedded Architectures
EWI-2720
IR-38172

Access to Document

10.1109/DSD.2002.1115354

http://doi.ieeecomputersociety.org/10.1109/DSD.2002.1115354

Cite this

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title = "The Synthesis of a Hardware Scheduler for Non-Manifest Loops",

abstract = "This paper addresses the hardware implementation of a dynamic scheduler for non-manifest data dependent periodic loops. Static scheduling techniques which are known to give near optimal scheduling-solutions for manifest loops, fail at scheduling non-manifest loops, since they lack the run time information needed which makes a static schedule feasible. In this paper a dynamic scheduling approach was chosen to circumvent this problem. We present a case study using VHDL were the focus lies on implementations with minimal memory usage and low communication overhead between various components of the architecture. This has resulted in an efficient and synthesisable system.",

keywords = "METIS-209133, CAES-EEA: Efficient Embedded Architectures, EWI-2720, IR-38172",

author = "O. Mansour and Egbert Molenkamp and Th. Krol",

year = "2002",

month = sep,

doi = "10.1109/DSD.2002.1115354",

language = "Undefined",

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AU - Mansour, O.

AU - Molenkamp, Egbert

AU - Krol, Th.

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PY - 2002/9

Y1 - 2002/9

N2 - This paper addresses the hardware implementation of a dynamic scheduler for non-manifest data dependent periodic loops. Static scheduling techniques which are known to give near optimal scheduling-solutions for manifest loops, fail at scheduling non-manifest loops, since they lack the run time information needed which makes a static schedule feasible. In this paper a dynamic scheduling approach was chosen to circumvent this problem. We present a case study using VHDL were the focus lies on implementations with minimal memory usage and low communication overhead between various components of the architecture. This has resulted in an efficient and synthesisable system.

AB - This paper addresses the hardware implementation of a dynamic scheduler for non-manifest data dependent periodic loops. Static scheduling techniques which are known to give near optimal scheduling-solutions for manifest loops, fail at scheduling non-manifest loops, since they lack the run time information needed which makes a static schedule feasible. In this paper a dynamic scheduling approach was chosen to circumvent this problem. We present a case study using VHDL were the focus lies on implementations with minimal memory usage and low communication overhead between various components of the architecture. This has resulted in an efficient and synthesisable system.

KW - METIS-209133

KW - CAES-EEA: Efficient Embedded Architectures

KW - EWI-2720

KW - IR-38172

U2 - 10.1109/DSD.2002.1115354

DO - 10.1109/DSD.2002.1115354

M3 - Conference contribution

SN - 0-7695-1790-0

SP - 78

EP - 85

BT - Euromicro Symposium on Digital System Design (DSD'02)

PB - IEEE

Y2 - 4 September 2002 through 6 September 2002

ER -