The Synthesis of a Hardware Scheduler for Non-Manifest Loops

O. Mansour, Egbert Molenkamp, Th. Krol

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    91 Downloads (Pure)

    Abstract

    This paper addresses the hardware implementation of a dynamic scheduler for non-manifest data dependent periodic loops. Static scheduling techniques which are known to give near optimal scheduling-solutions for manifest loops, fail at scheduling non-manifest loops, since they lack the run time information needed which makes a static schedule feasible. In this paper a dynamic scheduling approach was chosen to circumvent this problem. We present a case study using VHDL were the focus lies on implementations with minimal memory usage and low communication overhead between various components of the architecture. This has resulted in an efficient and synthesisable system.
    Original languageUndefined
    Title of host publicationEuromicro Symposium on Digital System Design (DSD'02)
    PublisherIEEE
    Pages78-85
    Number of pages8
    ISBN (Print)0-7695-1790-0
    DOIs
    Publication statusPublished - Sep 2002
    Event5th EUROMICRO Symposium on Digital System Design, DSD 2002 - Dortmund, Germany
    Duration: 4 Sep 20026 Sep 2002
    Conference number: 5

    Publication series

    Name
    PublisherIEEE

    Conference

    Conference5th EUROMICRO Symposium on Digital System Design, DSD 2002
    Abbreviated titleDSD
    CountryGermany
    CityDortmund
    Period4/09/026/09/02

    Keywords

    • METIS-209133
    • CAES-EEA: Efficient Embedded Architectures
    • EWI-2720
    • IR-38172

    Cite this