The time-voltage trade-off for ESD damage threshold in amorphous silicon hydrogenated thin film transistors

N. Golo-Tosic, S. van der Wal, F.G. Kuper, A.J. Mouthaan

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    It is investigated whether damage or breakdown of the amorphous silicon thin film transistors (alpha-Si:H TFT's) under pulsed stress depends on the stress time. The drain of grounded gate TFT's has been stressed applying repeated square voltage pulses of different duration (100ns to 10s). The evolution and the mechanisms of the pre-breakdown degradation will be presented and discussed. Finally, the temperature distribution across an alpha-Si:H TFT under applied stress will be simulated by means of coupled electro-thermal simulations.
    Original languageUndefined
    Article number10.1016/S0026-2714(01)00148-2
    Pages (from-to)1391-1396
    Number of pages6
    JournalMicroelectronics reliability
    Issue number9-10
    Publication statusPublished - 1 Oct 2001


    • IR-67774
    • EWI-15618

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