Abstract
Thermal phenomena occurring along test execution at the final stages of the manufacturing flow are considered as a significant issue for several reasons, including dramatic effects like circuit damage that is leading to yield loss. This paper tries to redeem those bad guys in order to exploit them to improve the test quality, reducing the overall test cost without affecting the yield.
Original language | Undefined |
---|---|
Title of host publication | IEEE 34th VLSI Test Symposium (VTS 2016) |
Place of Publication | USA |
Publisher | IEEE |
Pages | 1-4 |
Number of pages | 4 |
ISBN (Print) | 978-1-4673-8454-4 |
DOIs | |
Publication status | Published - Apr 2016 |
Event | 34th IEEE VLSI Test Symposium, VTS 2016 - Las Vegas, United States Duration: 25 Apr 2016 → 27 Apr 2016 Conference number: 34 |
Publication series
Name | |
---|---|
Publisher | IEEE |
Conference
Conference | 34th IEEE VLSI Test Symposium, VTS 2016 |
---|---|
Abbreviated title | VTS |
Country/Territory | United States |
City | Las Vegas |
Period | 25/04/16 → 27/04/16 |
Keywords
- CAES-TDT: Testable Design and Test
- EC Grant Agreement nr.: FP7/619871
- IR-101090
- METIS-318484
- EWI-27122