Skip to main navigation Skip to search Skip to main content

Three-Level Parallel PWM-Interleaved SiC Inverter With CMV Mitigation For Aerospace Applications

Research output: Contribution to journal › Article › Academic › peer-review

Abstract

In inverter-fed drive systems for aerospace applications, fast-switching voltage source inverters generate common-mode voltage (CMV) and common-mode current (CMI), making compliance with the DO-160G EMI standard challenging. In addition, output harmonics increase motor losses, while long inverter–load cables introduce parasitic elements that aggravate EMI behaviour and can induce overvoltage oscillations. Furthermore, aerospace systems impose stringent reliability requirements. This paper presents a three-level parallel PWM-interleaved silicon carbide (SiC) voltage source inverter with an active fourth leg (3LFVSI) aimed at simultaneously enabling converter-level cancellation of CMV under symmetric operating conditions, improving output waveform quality, and enabling post-fault operation in aerospace applications with an inaccessible neutral point. The proposed architecture employs parallel-interleaved two-level voltage source inverters (2LVSIs) together with an actively controlled fourth leg to enable effective CMV cancellation under symmetrical operating conditions. An integrated coupled inductor is introduced to simultaneously suppress circulating currents and provide the required output filter inductance within a compact magnetic structure. Furthermore, the impact of inverter dead time on practical CMV cancellation performance is analyzed and compensated. The proposed concept is validated through simulations and a 5 kW experimental prototype employing 1200 V SiC MOSFETs. The experimental results demonstrate converter-level suppression of common-mode current, achieving attenuation exceeding 32 dBμA below 400 kHz. In addition, the output filter reduces output voltage and current total harmonic distortion (THD), thereby mitigating overvoltage oscillations and motor losses. The converter also maintains operational capability under fault conditions by reconfiguring into a conventional 2LVSI while preserving CMV-mitigation functionality. The results demonstrate the viability of the proposed 3LFVSI as a converter architecture for aerospace inverter applications where CMV is addressed at the topology level.

Original languageEnglish
Number of pages19
JournalIEEE Journal of Emerging and Selected Topics in Power Electronics
DOIs
Publication statusE-pub ahead of print/First online - 29 May 2026

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

  1. SDG 7 - Affordable and Clean Energy
    SDG 7 Affordable and Clean Energy

Keywords

  • 2026 OA procedure
  • fault tolerance
  • interleaved inverter
  • more-electric aircraft
  • Multilevel inverter
  • wide-band gap devices
  • common-mode voltage

Fingerprint

Dive into the research topics of 'Three-Level Parallel PWM-Interleaved SiC Inverter With CMV Mitigation For Aerospace Applications'. Together they form a unique fingerprint.

Cite this