Throughput optimizations for FPGA-based deep neural network inference

Thorbjörn Posewsky, Daniel Ziener* (Corresponding Author)

*Corresponding author for this work

    Research output: Contribution to journalArticleAcademicpeer-review

    5 Citations (Scopus)
    52 Downloads (Pure)

    Abstract

    Deep neural networks are an extremely successful and widely used technique for various pattern recognition and machine learning tasks. Due to power and resource constraints, these computationally intensive networks are difficult to implement in embedded systems. Yet, the number of applications that can benefit from the mentioned possibilities is rapidly rising. In this paper, we propose novel architectures for the inference of previously learned and arbitrary deep neural networks on FPGA-based SoCs that are able to overcome these limitations. Our key contributions include the reuse of previously transferred weight matrices across multiple input samples, which we refer to as batch processing, and the usage of compressed weight matrices, also known as pruning. An extensive evaluation of these optimizations is presented. Both techniques allow a significant mitigation of data transfers and speed-up the network inference by one order of magnitude. At the same time, we surpass the data throughput of fully-featured x86-based systems while only using a fraction of their energy consumption.

    Original languageEnglish
    Pages (from-to)151-161
    Number of pages11
    JournalMicroprocessors and microsystems
    Volume60
    DOIs
    Publication statusPublished - 1 Jul 2018

    Keywords

    • Batch processing
    • Compression
    • Deep neural networks
    • FPGA
    • Fully-connected
    • Inference
    • Pruning
    • Throughput optimizations

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