Time Delay Circuits: A Quality Criterion for Delay Variations versus Frequency

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    Abstract

    This paper shows that the group delay of a delay circuit does not give sufficient information to predict the delay vs. frequency. A new criterion (fϕ=0) is proposed that characterizes the delay variations over a specified frequency range. The mathematical derivation of fϕ=0 for a single delay block and a cascade of delay blocks is shown. As examples the criterion is applied to the design of an RC and LC delay block. Delay predictions based on fϕ=0 are compared with simulation results, showing reasonable agreement.
    Original languageEnglish
    Title of host publicationProcedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2010)
    Place of PublicationPiscataway
    PublisherIEEE
    Pages4281-4284
    Number of pages4
    ISBN (Print)978-1-4244-5308-5
    DOIs
    Publication statusPublished - 2 Jun 2010
    EventIEEE International Symposium on Circuits and Systems, ISCAS 2010 - Paris, France
    Duration: 30 May 20102 Jun 2010

    Conference

    ConferenceIEEE International Symposium on Circuits and Systems, ISCAS 2010
    Abbreviated titleISCAS
    CountryFrance
    CityParis
    Period30/05/102/06/10

    Keywords

    • IR-75863
    • EWI-19460
    • METIS-276326

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  • Cite this

    Garakoui, S. K., Klumperink, E. A. M., Nauta, B., & van Vliet, F. E. (2010). Time Delay Circuits: A Quality Criterion for Delay Variations versus Frequency. In Procedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2010) (pp. 4281-4284). Piscataway: IEEE. https://doi.org/10.1109/ISCAS.2010.5537554