Time-interleaved Analog-to-Digital Converters

S.M. Louwsma

doi:10.3990/1.9789036529440

Time-interleaved Analog-to-Digital Converters

S.M. Louwsma

Research output: Thesis › PhD Thesis - Research UT, graduation UT

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Abstract

This thesis describes the feasibility of an analog-to-digital converter (ADC) with a sample-rate of 1-2 GS/s, a resolution of 8-10 bits, and a state-of-the-art power efficiency of less than 1 pJ/conversion step. The time-interleaved architecture exploits parallelism to increase the sample-rate while maintaining good power efficiency, and therefore it is the most suitable architecture.

Original language	Undefined
Awarding Institution	University of Twente
Supervisors/Advisors	van Tuijl, Adrianus Johannes Maria, Supervisor Nauta, Bram, Advisor
Thesis sponsors	Philips/NXP Research Laboratories
Award date	9 Dec 2009
Place of Publication	Enschede
Publisher	University of Twente
Print ISBNs	978-90-365-2944-0
DOIs	https://doi.org/10.3990/1.9789036529440
Publication status	Published - 9 Dec 2009

Keywords

IR-68690
EWI-17303
METIS-264496

Access to Document

10.3990/1.9789036529440

http://eprints.eemcs.utwente.nl/secure2/17303/01/thesis_S_Louwsma.pdf

Cite this

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AB - This thesis describes the feasibility of an analog-to-digital converter (ADC) with a sample-rate of 1-2 GS/s, a resolution of 8-10 bits, and a state-of-the-art power efficiency of less than 1 pJ/conversion step. The time-interleaved architecture exploits parallelism to increase the sample-rate while maintaining good power efficiency, and therefore it is the most suitable architecture.

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