Time-interleaved Analog-to-Digital Converters

S.M. Louwsma

    Research output: ThesisPhD Thesis - Research UT, graduation UT

    8 Downloads (Pure)


    This thesis describes the feasibility of an analog-to-digital converter (ADC) with a sample-rate of 1-2 GS/s, a resolution of 8-10 bits, and a state-of-the-art power efficiency of less than 1 pJ/conversion step. The time-interleaved architecture exploits parallelism to increase the sample-rate while maintaining good power efficiency, and therefore it is the most suitable architecture.
    Original languageUndefined
    Awarding Institution
    • University of Twente
    • van Tuijl, Adrianus Johannes Maria, Supervisor
    • Nauta, Bram, Advisor
    Thesis sponsors
    Award date9 Dec 2009
    Place of PublicationEnschede
    Print ISBNs978-90-365-2944-0
    Publication statusPublished - 9 Dec 2009


    • IR-68690
    • EWI-17303
    • METIS-264496

    Cite this