This thesis describes the feasibility of an analog-to-digital converter (ADC) with a sample-rate of 1-2 GS/s, a resolution of 8-10 bits, and a state-of-the-art power efficiency of less than 1 pJ/conversion step. The time-interleaved architecture exploits parallelism to increase the sample-rate while maintaining good power efficiency, and therefore it is the most suitable architecture.
|Award date||9 Dec 2009|
|Place of Publication||Enschede|
|Publication status||Published - 9 Dec 2009|