Time-interleaved high-speed D/A converters

E. Olieman

    Research output: ThesisPhD Thesis - Research UT, graduation UT

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    This thesis is on power efficient very high-speed digital-to-analog converters (DACs) in CMOS technology, intended to generate signals from DC to RF. Components in RF signal chains are nowadays often moved from the analog domain to the digital domain. This allows for more flexibility and better scaling of performance with new CMOS processes. The number of tasks in the transmit chain that can be moved to the digital domain depends on the performance of the available DACs. This thesis was performed as part of the STARS project, which is intended to develop the technologies required for reconfigurable radar systems. The flexibility and reconfigurability which is possible in the digital domain fits well within the scope of the project, which can be better exploited with improved DACs. The most widely used DAC implementation for high-speed operation is the current steering DAC. Its operating principles and its limitations are discussed in the introduction of this thesis, including some solutions reported in literature for these limitations. It is shown that the major error sources of conventional high-speed current steering DACs occur right at or after the switching instance, while for the majority of the DAC’s period, after its output is settled, the output is close to ideal. These switching related errors limit the signal frequency range and power efficiency of conventional DACs considerably. Interleaved current steering DACs, which are the topic of this thesis, are introduced to circumvent these performance-limiting switching related issues. The interleaved architecture consists of two sub-DACs that operate in parallel and an analog multiplexer that combines them into one output. The sDACs are regular current steering DACs, with limited performance due to their non-ideal behavior. After one of the sDACs is supplied with a new digital code, it gets some time to settle. During this time the other sDAC which operates at the opposite clock phase is connected to the output via the analog multiplexer. After the first sDAC is finished settling, the analog multiplexer toggles and connects that sDAC to the output. Meanwhile the second sDAC is supplied with a new digital code and gets time to settle its output. This architecture isolates the most dominant errors of the sDACs, which are centered around the switching instance, from the actual output. This interleaved architecture allows for better linearity for high-speed DACs, but it also has some inherent limitations that need to be taken into account. The analog multiplexer should be sufficiently linear, the full scale amplitude of the sDACs need to be similar, and also the duty cycle of the two sDACs need to be accurately defined. As described in chapter 3, code independent behavior of the analog multiplexer is achieved by employing triode switches instead of saturation switches. Also a method to measure the duty cycle error is introduced which only requires DC comparisons. In order to proof the viability of the interleaved architecture a 1.7GS/s, 12-bit DAC is designed that achieves better than 58dB SFDR over Nyquist while consuming 70mW. The individual current sources of the sDACs can be calibrated with a new method using only DC comparisons. The initial uncalibrated gain error between the two sDACs is over 60LSB, while after calibration this is reduced by a factor 150 to only 0.4LSB. A digital capacitor bank is included which is capable of adjusting the duty cycle to remove any duty cycle associated errors. The third order intermodulation products are reduced by almost 20dB when the interleaved output is compared to the direct output of the sDACs. Two more ICs are designed, both having 9-bit resolution, better than 50dB SFDR over Nyquist and close to 100mW power consumption. The first one is produced in 65nm CMOS and runs at 8.8GS/s, while the second one runs at 11GS/s and is produced in 28nm FDSOI. Their core area is very small: they occupy respectively 0.074mm2 and 0.04mm2. This power efficient high-speed operation is achieved by using quad-switching to further suppress unwanted code-dependent behavior. Their duty cycle can be adjusted using external tune voltages. All these demonstrator ICs show that despite requiring two separate sDACs, the introduced interleaved architecture is very suitable to design small, low-power DACs with good performance at very high sample rates.
    Original languageUndefined
    Awarding Institution
    • University of Twente
    • Nauta, Bram , Supervisor
    • Annema, Anne J., Advisor
    Thesis sponsors
    Award date2 Mar 2016
    Place of PublicationEnschede
    Print ISBNs978-90-365-4019-3
    Publication statusPublished - 2 Mar 2016


    • EWI-26912
    • IR-99674
    • METIS-316106

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