Timing verification of QCA memory architectures

M. Ottavi, L. Schiano, S. Pontarelli, V. Vankamamidi, F. Lombardi

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

6 Citations (Scopus)

Abstract

Quantum-dot Cellular Automata (QCA) provides a new functional paradigm for information processing and communication. In QCA the design of memories is substantially different from CMOS; several memory architectures have been proposed for QCA implementation. They have different logic and timing features in their operation. However, these architectures have not been fully verified due to limitations in current QCA design tools. This paper deals with the timing verification of three different memory architectures using simulation in HDL Verilog. Results are presented to confirm the viability and functional correctness of these memory architectures. This paper also shows that HDL based simulation is very effective for verification while allowing flexibility in modeling.
Original languageEnglish
Title of host publication2006 6th IEEE Conference on Nanotechnology, IEEE-NANO 2006
DOIs
Publication statusPublished - 2006
Externally publishedYes
Event6th IEEE Conference on Nanotechnology 2006 - Cincinnati, United States
Duration: 17 Jul 200620 Jul 2006
Conference number: 6

Conference

Conference6th IEEE Conference on Nanotechnology 2006
Country/TerritoryUnited States
CityCincinnati
Period17/07/0620/07/06

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