Timing verification of QCA memory architectures

Quantum-dot Cellular Automata (QCA) provides a new functional paradigm for information processing and communication. In QCA the design of memories is substantially different from CMOS; several memory architectures have been proposed for QCA implementation. They have different logic and timing features in their operation. However, these architectures have not been fully verified due to limitations in current QCA design tools. This paper deals with the timing verification of three different memory architectures using simulation in HDL Verilog. Results are presented to confirm the viability and functional correctness of these memory architectures. This paper also shows that HDL based simulation is very effective for verification while allowing flexibility in modeling.