Transmission Line Model Testing of Top-Gate Amorphous Silicon Thin Film Transistors

N. Tosic; F.G. Kuper; A.J. Mouthaan

doi:10.1109/RELPHY.2000.843929

Transmission Line Model Testing of Top-Gate Amorphous Silicon Thin Film Transistors

N. Tosic, F.G. Kuper, A.J. Mouthaan

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

12 Citations (Scopus)

199 Downloads (Pure)

Abstract

In this paper, for the first time Transmission Line Model (TLM) characterization is used to analyze ESD events in amorphous silicon thin film transistors (¿-Si:H TFT). It will be shown that, above an ESD degradation threshold voltage, deterioration of electrical characteristics sets in, and that above another ESD failure threshold voltage, dielectric breakdown occurs. Electrical simulations of an ¿-Si:H TFT confirm creation of positive interface charges as being the most likely cause of the deterioration process. Two failure modes have been identified by failure analysis

Original language	English
Title of host publication	2000 IEEE International Reliability Physics Symposium proceedings
Subtitle of host publication	38th annual : San Jose, California, April 10-13, 2000
Place of Publication	Piscataway, NJ
Publisher	IEEE
Pages	289-294
ISBN (Print)	9780780358607, 9780780358614
DOIs	https://doi.org/10.1109/RELPHY.2000.843929
Publication status	Published - 1 Jan 2000
Event	38th Annual IEEE International Reliability Physics Symposium, IRPS 2000 - San Jose, United States Duration: 10 Apr 2000 → 13 Apr 2000 Conference number: 38

Conference

Conference	38th Annual IEEE International Reliability Physics Symposium, IRPS 2000
Abbreviated title	IRPS
Country/Territory	United States
City	San Jose
Period	10/04/00 → 13/04/00

Keywords

IR-17064
METIS-113950

Access to Document

10.1109/RELPHY.2000.843929

Transmission_line_model_-_tosic

Cite this

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title = "Transmission Line Model Testing of Top-Gate Amorphous Silicon Thin Film Transistors",

abstract = "In this paper, for the first time Transmission Line Model (TLM) characterization is used to analyze ESD events in amorphous silicon thin film transistors (¿-Si:H TFT). It will be shown that, above an ESD degradation threshold voltage, deterioration of electrical characteristics sets in, and that above another ESD failure threshold voltage, dielectric breakdown occurs. Electrical simulations of an ¿-Si:H TFT confirm creation of positive interface charges as being the most likely cause of the deterioration process. Two failure modes have been identified by failure analysis",

keywords = "IR-17064, METIS-113950",

author = "N. Tosic and F.G. Kuper and A.J. Mouthaan",

year = "2000",

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doi = "10.1109/RELPHY.2000.843929",

language = "English",

isbn = "9780780358607",

pages = "289--294",

booktitle = "2000 IEEE International Reliability Physics Symposium proceedings",

publisher = "IEEE",

address = "United States",

note = "38th Annual IEEE International Reliability Physics Symposium, IRPS 2000, IRPS ; Conference date: 10-04-2000 Through 13-04-2000",

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Tosic, N, Kuper, FG & Mouthaan, AJ 2000, Transmission Line Model Testing of Top-Gate Amorphous Silicon Thin Film Transistors. in 2000 IEEE International Reliability Physics Symposium proceedings: 38th annual : San Jose, California, April 10-13, 2000. IEEE, Piscataway, NJ, pp. 289-294, 38th Annual IEEE International Reliability Physics Symposium, IRPS 2000, San Jose, California, United States, 10/04/00. https://doi.org/10.1109/RELPHY.2000.843929

Transmission Line Model Testing of Top-Gate Amorphous Silicon Thin Film Transistors. / Tosic, N.; Kuper, F.G.; Mouthaan, A.J.
2000 IEEE International Reliability Physics Symposium proceedings: 38th annual : San Jose, California, April 10-13, 2000. Piscataway, NJ: IEEE, 2000. p. 289-294.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Transmission Line Model Testing of Top-Gate Amorphous Silicon Thin Film Transistors

AU - Tosic, N.

AU - Kuper, F.G.

AU - Mouthaan, A.J.

N1 - Conference code: 38

PY - 2000/1/1

Y1 - 2000/1/1

N2 - In this paper, for the first time Transmission Line Model (TLM) characterization is used to analyze ESD events in amorphous silicon thin film transistors (¿-Si:H TFT). It will be shown that, above an ESD degradation threshold voltage, deterioration of electrical characteristics sets in, and that above another ESD failure threshold voltage, dielectric breakdown occurs. Electrical simulations of an ¿-Si:H TFT confirm creation of positive interface charges as being the most likely cause of the deterioration process. Two failure modes have been identified by failure analysis

AB - In this paper, for the first time Transmission Line Model (TLM) characterization is used to analyze ESD events in amorphous silicon thin film transistors (¿-Si:H TFT). It will be shown that, above an ESD degradation threshold voltage, deterioration of electrical characteristics sets in, and that above another ESD failure threshold voltage, dielectric breakdown occurs. Electrical simulations of an ¿-Si:H TFT confirm creation of positive interface charges as being the most likely cause of the deterioration process. Two failure modes have been identified by failure analysis

KW - IR-17064

KW - METIS-113950

U2 - 10.1109/RELPHY.2000.843929

DO - 10.1109/RELPHY.2000.843929

M3 - Conference contribution

SN - 9780780358607

SN - 9780780358614

SP - 289

EP - 294

BT - 2000 IEEE International Reliability Physics Symposium proceedings

PB - IEEE

CY - Piscataway, NJ

T2 - 38th Annual IEEE International Reliability Physics Symposium, IRPS 2000

Y2 - 10 April 2000 through 13 April 2000

ER -

Transmission Line Model Testing of Top-Gate Amorphous Silicon Thin Film Transistors

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