Transmission Line Model Testing of Top-Gate Amorphous Silicon Thin Film Transistors

N. Tosic, F.G. Kuper, A.J. Mouthaan

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    9 Citations (Scopus)
    78 Downloads (Pure)

    Abstract

    In this paper, for the first time Transmission Line Model (TLM) characterization is used to analyze ESD events in amorphous silicon thin film transistors (¿-Si:H TFT). It will be shown that, above an ESD degradation threshold voltage, deterioration of electrical characteristics sets in, and that above another ESD failure threshold voltage, dielectric breakdown occurs. Electrical simulations of an ¿-Si:H TFT confirm creation of positive interface charges as being the most likely cause of the deterioration process. Two failure modes have been identified by failure analysis
    Original languageEnglish
    Title of host publication2000 IEEE International Reliability Physics Symposium proceedings
    Subtitle of host publication38th annual : San Jose, California, April 10-13, 2000
    Place of PublicationPiscataway, NJ
    PublisherIEEE
    Pages289-294
    ISBN (Print)9780780358607, 9780780358614
    DOIs
    Publication statusPublished - 1 Jan 2000
    Event38th Annual IEEE International Reliability Physics Symposium, IRPS 2000 - San Jose, United States
    Duration: 10 Apr 200013 Apr 2000
    Conference number: 38

    Conference

    Conference38th Annual IEEE International Reliability Physics Symposium, IRPS 2000
    Abbreviated titleIRPS
    CountryUnited States
    CitySan Jose
    Period10/04/0013/04/00

    Keywords

    • IR-17064
    • METIS-113950

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  • Cite this

    Tosic, N., Kuper, F. G., & Mouthaan, A. J. (2000). Transmission Line Model Testing of Top-Gate Amorphous Silicon Thin Film Transistors. In 2000 IEEE International Reliability Physics Symposium proceedings: 38th annual : San Jose, California, April 10-13, 2000 (pp. 289-294). Piscataway, NJ: IEEE. https://doi.org/10.1109/RELPHY.2000.843929