Trends and challenges in VLSI technology scaling towards 100 nm

Stefan Rusu, Manoj Sachdev, Christer Svensson, Bram Nauta

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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    Summary form only given. Moore's Law drives VLSI technology to continuous increases in transistor densities and higher clock frequencies. This tutorial will review the trends in VLSI technology scaling in the last few years and discuss the challenges facing process and circuit engineers in the 100nm generation and beyond. The first focus area is the process technology, including transistor scaling trends and research activities for the 100nm technology node and beyond. The transistor leakage and interconnect RC delays will continue to increase. The tutorial will review new circuit design techniques for emerging process technologies, including dual Vt transistors and silicon-on-insulator. It will also cover circuit and layout techniques to reduce clock distribution skew and jitter, model and reduce transistor leakage and improve the electrical performance of flip-chip packages. Finally, the tutorial will review the test challenges for the 100nm technology node due to increased clock frequency and power consumption (both active and passive) and present several potential solutions
    Original languageEnglish
    Title of host publicationProceedings of ASP-DAC/VLSI Design 2002
    Subtitle of host publication7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design
    Number of pages2
    ISBN (Print)0-7695-1441-3
    Publication statusPublished - Jan 2002
    Event39th Annual Design Automation Conference, DAC 2002 - New Orleans, United States
    Duration: 10 Jun 200214 Jun 2002
    Conference number: 39


    Conference39th Annual Design Automation Conference, DAC 2002
    Abbreviated titleDAC 2002
    Country/TerritoryUnited States
    CityNew Orleans


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