Abstract
| Original language | English |
|---|---|
| Pages (from-to) | 1370-1382 |
| Number of pages | 13 |
| Journal | IEEE journal of solid-state circuits |
| Volume | 48 |
| Issue number | 6 |
| DOIs | |
| Publication status | Published - 1 Jun 2013 |
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Keywords
- EWI-23470
- METIS-297713
- IR-86403
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Tunable n-path notch filters for blocker suppression : modeling and verification. / Ghaffari, Amir; Klumperink, Eric A.M.; Nauta, Bram.
In: IEEE journal of solid-state circuits, Vol. 48, No. 6, 01.06.2013, p. 1370-1382.Research output: Contribution to journal › Article › Academic › peer-review
TY - JOUR
T1 - Tunable n-path notch filters for blocker suppression
T2 - modeling and verification
AU - Ghaffari, Amir
AU - Klumperink, Eric A.M.
AU - Nauta, Bram
N1 - eemcs-eprint-23470
PY - 2013/6/1
Y1 - 2013/6/1
N2 - N-path switched-RC circuits can realize filters with very high linearity and compression point while they are tunable by a clock frequency. In this paper, both differential and single-ended N-path notch filters are modeled and analyzed. Closed-form equations provide design equations for the main filtering characteristics and nonidealities such as: harmonic mixing, switch resistance, mismatch and phase imbalance, clock rise and fall times, noise, and insertion loss. Both an eight-path single-ended and differential notch filter are implemented in 65-nm CMOS technology. The notch center frequency, which is determined by the switching frequency, is tunable from 0.1 to 1.2 GHz. In a 50- environment, the N-path filters provide power matching in the passband with an insertion loss of 1.4–2.8 dB. The rejection at the notch frequency is 21–24 dB,P1 db> + 2 dBm, and IIP3 > + 17 dBm.
AB - N-path switched-RC circuits can realize filters with very high linearity and compression point while they are tunable by a clock frequency. In this paper, both differential and single-ended N-path notch filters are modeled and analyzed. Closed-form equations provide design equations for the main filtering characteristics and nonidealities such as: harmonic mixing, switch resistance, mismatch and phase imbalance, clock rise and fall times, noise, and insertion loss. Both an eight-path single-ended and differential notch filter are implemented in 65-nm CMOS technology. The notch center frequency, which is determined by the switching frequency, is tunable from 0.1 to 1.2 GHz. In a 50- environment, the N-path filters provide power matching in the passband with an insertion loss of 1.4–2.8 dB. The rejection at the notch frequency is 21–24 dB,P1 db> + 2 dBm, and IIP3 > + 17 dBm.
KW - EWI-23470
KW - METIS-297713
KW - IR-86403
U2 - 10.1109/JSSC.2013.2252521
DO - 10.1109/JSSC.2013.2252521
M3 - Article
VL - 48
SP - 1370
EP - 1382
JO - IEEE journal of solid-state circuits
JF - IEEE journal of solid-state circuits
SN - 0018-9200
IS - 6
ER -