Turn-on speed of grounded gate NMOS ESD protection transistors

G. Meneghesso; J.R.M. Luchies; F.G. Kuper; A.J. Mouthaan

doi:10.1016/0026-2714(96)00186-2

Turn-on speed of grounded gate NMOS ESD protection transistors

G. Meneghesso
, J.R.M. Luchies
, F.G. Kuper
, A.J. Mouthaan

Research output: Contribution to journal › Article › Academic › peer-review

11 Citations (Scopus)

243 Downloads (Pure)

Abstract

The turn-on speed of nMOS transistors (nMOST) is of paramount importance for robust Charged Device Model (CDM) protection circuitry. In this paper the nMOST turn-on time has been measured for the first time in the sub-halve nanosecond range with a commercial e-beam tester. The method may be used to improve CDM-ESD hardness by investigating the CDM pulse responses within circuit. Furthermore it is shown that the CDM results of various protection layouts can be simulated with a SPICE model.

Original language	English
Pages (from-to)	1735-1738
Journal	Microelectronics reliability
Volume	36
Issue number	11/12
DOIs	https://doi.org/10.1016/0026-2714(96)00186-2
Publication status	Published - 1996
Event	7th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, ESREF 1996 - University of Twente, Enschede, Netherlands Duration: 8 Oct 1996 → 11 Oct 1996 Conference number: 7

Keywords

METIS-111996
IR-15124

Access to Document

10.1016/0026-2714(96)00186-2

Meneghesso96turn

Cite this

@article{e9e1bb445131474582cb7858a875cde9,

title = "Turn-on speed of grounded gate NMOS ESD protection transistors",

abstract = "The turn-on speed of nMOS transistors (nMOST) is of paramount importance for robust Charged Device Model (CDM) protection circuitry. In this paper the nMOST turn-on time has been measured for the first time in the sub-halve nanosecond range with a commercial e-beam tester. The method may be used to improve CDM-ESD hardness by investigating the CDM pulse responses within circuit. Furthermore it is shown that the CDM results of various protection layouts can be simulated with a SPICE model.",

keywords = "METIS-111996, IR-15124",

author = "G. Meneghesso and J.R.M. Luchies and F.G. Kuper and A.J. Mouthaan",

year = "1996",

doi = "10.1016/0026-2714(96)00186-2",

language = "English",

volume = "36",

pages = "1735--1738",

journal = "Microelectronics reliability",

issn = "0026-2714",

publisher = "Elsevier",

number = "11/12",

note = "7th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, ESREF 1996, ESREF ; Conference date: 08-10-1996 Through 11-10-1996",

}

TY - JOUR

T1 - Turn-on speed of grounded gate NMOS ESD protection transistors

AU - Meneghesso, G.

AU - Luchies, J.R.M.

AU - Kuper, F.G.

AU - Mouthaan, A.J.

N1 - Conference code: 7

PY - 1996

Y1 - 1996

N2 - The turn-on speed of nMOS transistors (nMOST) is of paramount importance for robust Charged Device Model (CDM) protection circuitry. In this paper the nMOST turn-on time has been measured for the first time in the sub-halve nanosecond range with a commercial e-beam tester. The method may be used to improve CDM-ESD hardness by investigating the CDM pulse responses within circuit. Furthermore it is shown that the CDM results of various protection layouts can be simulated with a SPICE model.

AB - The turn-on speed of nMOS transistors (nMOST) is of paramount importance for robust Charged Device Model (CDM) protection circuitry. In this paper the nMOST turn-on time has been measured for the first time in the sub-halve nanosecond range with a commercial e-beam tester. The method may be used to improve CDM-ESD hardness by investigating the CDM pulse responses within circuit. Furthermore it is shown that the CDM results of various protection layouts can be simulated with a SPICE model.

KW - METIS-111996

KW - IR-15124

U2 - 10.1016/0026-2714(96)00186-2

DO - 10.1016/0026-2714(96)00186-2

M3 - Article

SN - 0026-2714

VL - 36

SP - 1735

EP - 1738

JO - Microelectronics reliability

JF - Microelectronics reliability

IS - 11/12

T2 - 7th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, ESREF 1996

Y2 - 8 October 1996 through 11 October 1996

ER -

Turn-on speed of grounded gate NMOS ESD protection transistors

Abstract

Keywords

Access to Document

Fingerprint

Cite this