This paper compares the implementation results of two architectures for virtual channel router. Since the router is used for building an on-chip network, its small size is critical. Together with the total design area we provide information about the distribution of this area between the main router blocks and thus give insight about the cost of each block. The comparison shows that one of the architectures results in smaller implementation area and overcomes some performance problems presented by the other architecture.
|Title of host publication||5th PROGRESS Symposium on Embedded Systems|
|Place of Publication||Utrecht, The Netherlands|
|Number of pages||6|
|Publication status||Published - Oct 2004|
|Event||5th PROGRESS Symposium on Embedded Systems 2004 - Nieuwegein, Netherlands|
Duration: 20 Oct 2004 → 20 Oct 2004
Conference number: 5
|Publisher||STW Technology Foundation|
|Conference||5th PROGRESS Symposium on Embedded Systems 2004|
|Period||20/10/04 → 20/10/04|
- CAES-EEA: Efficient Embedded Architectures
Kavaldjiev, N. K., Smit, G. J. M., & Jansen, P. G. (2004). Two Architectures for On-chip Virtual Channel Router. In 5th PROGRESS Symposium on Embedded Systems (pp. 90-95). Utrecht, The Netherlands: STW.