Two Architectures for On-chip Virtual Channel Router

N.K. Kavaldjiev, Gerardus Johannes Maria Smit, P.G. Jansen

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    Abstract

    This paper compares the implementation results of two architectures for virtual channel router. Since the router is used for building an on-chip network, its small size is critical. Together with the total design area we provide information about the distribution of this area between the main router blocks and thus give insight about the cost of each block. The comparison shows that one of the architectures results in smaller implementation area and overcomes some performance problems presented by the other architecture.
    Original languageUndefined
    Title of host publication5th PROGRESS Symposium on Embedded Systems
    Place of PublicationUtrecht, The Netherlands
    PublisherSTW
    Pages90-95
    Number of pages6
    ISBN (Print)90-73461-41-3
    Publication statusPublished - Oct 2004
    Event5th PROGRESS Symposium on Embedded Systems 2004 - Nieuwegein, Netherlands
    Duration: 20 Oct 200420 Oct 2004
    Conference number: 5

    Publication series

    Name
    PublisherSTW Technology Foundation

    Conference

    Conference5th PROGRESS Symposium on Embedded Systems 2004
    Abbreviated titlePROGRESS
    CountryNetherlands
    CityNieuwegein
    Period20/10/0420/10/04

    Keywords

    • METIS-221675
    • EWI-776
    • IR-49388
    • CAES-EEA: Efficient Embedded Architectures

    Cite this

    Kavaldjiev, N. K., Smit, G. J. M., & Jansen, P. G. (2004). Two Architectures for On-chip Virtual Channel Router. In 5th PROGRESS Symposium on Embedded Systems (pp. 90-95). Utrecht, The Netherlands: STW.