Two dimensional FFT architecture based on radix-43 algorithm with efficient output reordering

S. Kala; S. Nalesh; B.R. Jose; J. Mathew; M. Ottavi

doi:10.1109/DTIS.2018.8368562

Two dimensional FFT architecture based on radix-43 algorithm with efficient output reordering

S. Kala, S. Nalesh, B.R. Jose, J. Mathew, M. Ottavi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

1 Citation (Scopus)

Abstract

In this paper we present a 64 × 64-point 2D FFT architecture using a parallel unrolled radix-4 3 (R4 3 ) FFT as the basic block. Our R4 3 architecture is a memory optimized parallel architecture which computes 64-point FFT, with least execution time. Here we use row-column decomposition of two R4 3 blocks to compute a 2D FFT. Proposed architecture has been implemented in UMC 40nm CMOS technology with clock frequency of 500 MHz, area of 0.841mm 2 and power consumption of 358 mW. Computation time of 64 × 64 FFT is 8.19μs. ASIC results shows better performance of our FFT in terms of computation time when compared with state-of-art implementation.

Original language	English
Title of host publication	Proceedings - 2018 13th IEEE International Conference on Design and Technology of Integrated Systems In Nanoscale Era, DTIS 2018
DOIs	https://doi.org/10.1109/DTIS.2018.8368562
Publication status	Published - 2018
Externally published	Yes
Event	13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, DTIS 2018 - Taormina, Italy Duration: 9 Apr 2018 → 12 Apr 2018 Conference number: 13

Conference

Conference	13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, DTIS 2018
Abbreviated title	DTIS 2018
Country/Territory	Italy
City	Taormina
Period	9/04/18 → 12/04/18

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10.1109/DTIS.2018.8368562

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@inproceedings{02cc3b523c9941bc8431210c7414edfd,

title = "Two dimensional FFT architecture based on radix-43 algorithm with efficient output reordering",

abstract = "In this paper we present a 64 × 64-point 2D FFT architecture using a parallel unrolled radix-4 3 (R4 3 ) FFT as the basic block. Our R4 3 architecture is a memory optimized parallel architecture which computes 64-point FFT, with least execution time. Here we use row-column decomposition of two R4 3 blocks to compute a 2D FFT. Proposed architecture has been implemented in UMC 40nm CMOS technology with clock frequency of 500 MHz, area of 0.841mm 2 and power consumption of 358 mW. Computation time of 64 × 64 FFT is 8.19μs. ASIC results shows better performance of our FFT in terms of computation time when compared with state-of-art implementation.",

author = "S. Kala and S. Nalesh and B.R. Jose and J. Mathew and M. Ottavi",

year = "2018",

doi = "10.1109/DTIS.2018.8368562",

language = "English",

booktitle = "Proceedings - 2018 13th IEEE International Conference on Design and Technology of Integrated Systems In Nanoscale Era, DTIS 2018",

note = "13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, DTIS 2018, DTIS 2018 ; Conference date: 09-04-2018 Through 12-04-2018",

}

Kala, S, Nalesh, S, Jose, BR, Mathew, J & Ottavi, M 2018, Two dimensional FFT architecture based on radix-43 algorithm with efficient output reordering. in Proceedings - 2018 13th IEEE International Conference on Design and Technology of Integrated Systems In Nanoscale Era, DTIS 2018. 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, DTIS 2018, Taormina, Italy, 9/04/18. https://doi.org/10.1109/DTIS.2018.8368562

Two dimensional FFT architecture based on radix-43 algorithm with efficient output reordering. / Kala, S.; Nalesh, S.; Jose, B.R. et al.
Proceedings - 2018 13th IEEE International Conference on Design and Technology of Integrated Systems In Nanoscale Era, DTIS 2018. 2018.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Two dimensional FFT architecture based on radix-43 algorithm with efficient output reordering

AU - Kala, S.

AU - Nalesh, S.

AU - Jose, B.R.

AU - Mathew, J.

AU - Ottavi, M.

N1 - Conference code: 13

PY - 2018

Y1 - 2018

N2 - In this paper we present a 64 × 64-point 2D FFT architecture using a parallel unrolled radix-4 3 (R4 3 ) FFT as the basic block. Our R4 3 architecture is a memory optimized parallel architecture which computes 64-point FFT, with least execution time. Here we use row-column decomposition of two R4 3 blocks to compute a 2D FFT. Proposed architecture has been implemented in UMC 40nm CMOS technology with clock frequency of 500 MHz, area of 0.841mm 2 and power consumption of 358 mW. Computation time of 64 × 64 FFT is 8.19μs. ASIC results shows better performance of our FFT in terms of computation time when compared with state-of-art implementation.

AB - In this paper we present a 64 × 64-point 2D FFT architecture using a parallel unrolled radix-4 3 (R4 3 ) FFT as the basic block. Our R4 3 architecture is a memory optimized parallel architecture which computes 64-point FFT, with least execution time. Here we use row-column decomposition of two R4 3 blocks to compute a 2D FFT. Proposed architecture has been implemented in UMC 40nm CMOS technology with clock frequency of 500 MHz, area of 0.841mm 2 and power consumption of 358 mW. Computation time of 64 × 64 FFT is 8.19μs. ASIC results shows better performance of our FFT in terms of computation time when compared with state-of-art implementation.

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U2 - 10.1109/DTIS.2018.8368562

DO - 10.1109/DTIS.2018.8368562

M3 - Conference contribution

BT - Proceedings - 2018 13th IEEE International Conference on Design and Technology of Integrated Systems In Nanoscale Era, DTIS 2018

T2 - 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, DTIS 2018

Y2 - 9 April 2018 through 12 April 2018

ER -

Two dimensional FFT architecture based on radix-43 algorithm with efficient output reordering

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