Two-level pipelined systolic array graphics engine

J.A.K.S. Jayasinghe; G. Karagiannis; F. Moelaert El-Hadidy; O.E. Herrmann; J. Smit

doi:10.1109/CICC.1990.124759

Two-level pipelined systolic array graphics engine

J.A.K.S. Jayasinghe, G. Karagiannis, F. Moelaert El-Hadidy, O.E. Herrmann, J. Smit

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

A silicon implementation of a two-level pipelined SAG (systolic array graphics) engine supporting an advanced instructions set is reported. The advantage of the two-level pipelining is that it can provide a complex functionality at high pixel rates, which is difficult to achieve by other means using less silicon area. As computer graphics users have a great desire for high image quality, high interaction speed and high resolution, it is expected that two-level pipelined SAG engines will be a breakthrough for real-time computer graphics

Original language	English
Title of host publication	IEEE Proceedings of the Custom Integrated Circuits Conference 1990
Place of Publication	Piscataway, NJ
Publisher	IEEE
Number of pages	4
DOIs	https://doi.org/10.1109/CICC.1990.124759
Publication status	Published - 1 May 1990
Event	IEEE Custom Integrated Circuits Conference, CICC 1990 - Boston, United States Duration: 13 May 1990 → 16 May 1990

Conference

Conference	IEEE Custom Integrated Circuits Conference, CICC 1990
Abbreviated title	CICC
Country/Territory	United States
City	Boston
Period	13/05/90 → 16/05/90

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10.1109/CICC.1990.124759

Jayasinghe1990two-levelFinal published version, 339 KB

Cite this

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title = "Two-level pipelined systolic array graphics engine",

abstract = "A silicon implementation of a two-level pipelined SAG (systolic array graphics) engine supporting an advanced instructions set is reported. The advantage of the two-level pipelining is that it can provide a complex functionality at high pixel rates, which is difficult to achieve by other means using less silicon area. As computer graphics users have a great desire for high image quality, high interaction speed and high resolution, it is expected that two-level pipelined SAG engines will be a breakthrough for real-time computer graphics",

author = "J.A.K.S. Jayasinghe and G. Karagiannis and {Moelaert El-Hadidy}, F. and O.E. Herrmann and J. Smit",

year = "1990",

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booktitle = "IEEE Proceedings of the Custom Integrated Circuits Conference 1990",

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Jayasinghe, JAKS, Karagiannis, G, Moelaert El-Hadidy, F, Herrmann, OE & Smit, J 1990, Two-level pipelined systolic array graphics engine. in IEEE Proceedings of the Custom Integrated Circuits Conference 1990., 17.2, IEEE, Piscataway, NJ, IEEE Custom Integrated Circuits Conference, CICC 1990, Boston, Massachusetts, United States, 13/05/90. https://doi.org/10.1109/CICC.1990.124759

TY - GEN

T1 - Two-level pipelined systolic array graphics engine

AU - Jayasinghe, J.A.K.S.

AU - Karagiannis, G.

AU - Moelaert El-Hadidy, F.

AU - Herrmann, O.E.

AU - Smit, J.

PY - 1990/5/1

Y1 - 1990/5/1

N2 - A silicon implementation of a two-level pipelined SAG (systolic array graphics) engine supporting an advanced instructions set is reported. The advantage of the two-level pipelining is that it can provide a complex functionality at high pixel rates, which is difficult to achieve by other means using less silicon area. As computer graphics users have a great desire for high image quality, high interaction speed and high resolution, it is expected that two-level pipelined SAG engines will be a breakthrough for real-time computer graphics

AB - A silicon implementation of a two-level pipelined SAG (systolic array graphics) engine supporting an advanced instructions set is reported. The advantage of the two-level pipelining is that it can provide a complex functionality at high pixel rates, which is difficult to achieve by other means using less silicon area. As computer graphics users have a great desire for high image quality, high interaction speed and high resolution, it is expected that two-level pipelined SAG engines will be a breakthrough for real-time computer graphics

U2 - 10.1109/CICC.1990.124759

DO - 10.1109/CICC.1990.124759

M3 - Conference contribution

BT - IEEE Proceedings of the Custom Integrated Circuits Conference 1990

PB - IEEE

CY - Piscataway, NJ

T2 - IEEE Custom Integrated Circuits Conference, CICC 1990

Y2 - 13 May 1990 through 16 May 1990

ER -

Two-level pipelined systolic array graphics engine

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