Two-level pipelined systolic array graphics engine

J.A.K.S. Jayasinghe; G. Karagiannis; F. Moelaert El-Hadidy; O.E. Herrmann; J. Smit

doi:10.1109/CICC.1990.124759

Two-level pipelined systolic array graphics engine

J.A.K.S. Jayasinghe, G. Karagiannis, F. Moelaert El-Hadidy, O.E. Herrmann, J. Smit

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

A silicon implementation of a two-level pipelined SAG (systolic array graphics) engine supporting an advanced instructions set is reported. The advantage of the two-level pipelining is that it can provide a complex functionality at high pixel rates, which is difficult to achieve by other means using less silicon area. As computer graphics users have a great desire for high image quality, high interaction speed and high resolution, it is expected that two-level pipelined SAG engines will be a breakthrough for real-time computer graphics

Original language	English
Title of host publication	IEEE Proceedings of the Custom Integrated Circuits Conference 1990
Place of Publication	Piscataway, NJ
Publisher	IEEE
Number of pages	4
DOIs	https://doi.org/10.1109/CICC.1990.124759
Publication status	Published - 1 May 1990
Event	IEEE Custom Integrated Circuits Conference, CICC 1990 - Boston, United States Duration: 13 May 1990 → 16 May 1990

Conference

Conference	IEEE Custom Integrated Circuits Conference, CICC 1990
Abbreviated title	CICC
Country	United States
City	Boston
Period	13/05/90 → 16/05/90

Access to Document

10.1109/CICC.1990.124759

Jayasinghe1990two-level
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Final published version, 339 KB

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AU - Smit, J.

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