Two-Level Pipepined Systolic Array Graphics Engine

J.A.K.S. Jayasinghe, J.A.K.S. Jayasinghe, F. Moelaert El Hadidy, F. El hadidy, Georgios Karagiannis, O.E. Herrmann, Jaap Smit

Research output: Contribution to journalArticleAcademicpeer-review

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Abstract

The authors report a VLSI design of an advanced systolic array graphics (SAG) engine built from pipelined functional units which can generate realistic images interactively for high-resolution displays. They introduce a structured frame store system as an environment for the advanced SAG engine and present the principles and architecture of the advanced SAG engine. They introduce pipelined functional units into this SAG engine to meet the performance requirements. This is done by a formal approach where the original systolic array is represented at bit level by a finite, vertex-weighted, edge-weighted, directed graph. Two architectures built from pipelined functional units are described. A prototype containing nine processing elements was fabricated in a 1.6-¿m CMOS technology
Original languageUndefined
Pages (from-to)229-236
Number of pages8
JournalIEEE journal of solid-state circuits
Volume26
Issue number3
DOIs
Publication statusPublished - 1991

Keywords

  • METIS-111728
  • IR-14668
  • CMOS integrated circuits
  • digital signal processing chips
  • Pipeline processing
  • Systolic arrays
  • VLSI

Cite this

Jayasinghe, J. A. K. S., Jayasinghe, J. A. K. S., El Hadidy, F. M., El hadidy, F., Karagiannis, G., Herrmann, O. E., & Smit, J. (1991). Two-Level Pipepined Systolic Array Graphics Engine. IEEE journal of solid-state circuits, 26(3), 229-236. https://doi.org/10.1109/4.75000
Jayasinghe, J.A.K.S. ; Jayasinghe, J.A.K.S. ; El Hadidy, F. Moelaert ; El hadidy, F. ; Karagiannis, Georgios ; Herrmann, O.E. ; Smit, Jaap. / Two-Level Pipepined Systolic Array Graphics Engine. In: IEEE journal of solid-state circuits. 1991 ; Vol. 26, No. 3. pp. 229-236.
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abstract = "The authors report a VLSI design of an advanced systolic array graphics (SAG) engine built from pipelined functional units which can generate realistic images interactively for high-resolution displays. They introduce a structured frame store system as an environment for the advanced SAG engine and present the principles and architecture of the advanced SAG engine. They introduce pipelined functional units into this SAG engine to meet the performance requirements. This is done by a formal approach where the original systolic array is represented at bit level by a finite, vertex-weighted, edge-weighted, directed graph. Two architectures built from pipelined functional units are described. A prototype containing nine processing elements was fabricated in a 1.6-¿m CMOS technology",
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author = "J.A.K.S. Jayasinghe and J.A.K.S. Jayasinghe and {El Hadidy}, {F. Moelaert} and {El hadidy}, F. and Georgios Karagiannis and O.E. Herrmann and Jaap Smit",
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Jayasinghe, JAKS, Jayasinghe, JAKS, El Hadidy, FM, El hadidy, F, Karagiannis, G, Herrmann, OE & Smit, J 1991, 'Two-Level Pipepined Systolic Array Graphics Engine' IEEE journal of solid-state circuits, vol. 26, no. 3, pp. 229-236. https://doi.org/10.1109/4.75000

Two-Level Pipepined Systolic Array Graphics Engine. / Jayasinghe, J.A.K.S.; Jayasinghe, J.A.K.S.; El Hadidy, F. Moelaert; El hadidy, F.; Karagiannis, Georgios; Herrmann, O.E.; Smit, Jaap.

In: IEEE journal of solid-state circuits, Vol. 26, No. 3, 1991, p. 229-236.

Research output: Contribution to journalArticleAcademicpeer-review

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T1 - Two-Level Pipepined Systolic Array Graphics Engine

AU - Jayasinghe, J.A.K.S.

AU - Jayasinghe, J.A.K.S.

AU - El Hadidy, F. Moelaert

AU - El hadidy, F.

AU - Karagiannis, Georgios

AU - Herrmann, O.E.

AU - Smit, Jaap

PY - 1991

Y1 - 1991

N2 - The authors report a VLSI design of an advanced systolic array graphics (SAG) engine built from pipelined functional units which can generate realistic images interactively for high-resolution displays. They introduce a structured frame store system as an environment for the advanced SAG engine and present the principles and architecture of the advanced SAG engine. They introduce pipelined functional units into this SAG engine to meet the performance requirements. This is done by a formal approach where the original systolic array is represented at bit level by a finite, vertex-weighted, edge-weighted, directed graph. Two architectures built from pipelined functional units are described. A prototype containing nine processing elements was fabricated in a 1.6-¿m CMOS technology

AB - The authors report a VLSI design of an advanced systolic array graphics (SAG) engine built from pipelined functional units which can generate realistic images interactively for high-resolution displays. They introduce a structured frame store system as an environment for the advanced SAG engine and present the principles and architecture of the advanced SAG engine. They introduce pipelined functional units into this SAG engine to meet the performance requirements. This is done by a formal approach where the original systolic array is represented at bit level by a finite, vertex-weighted, edge-weighted, directed graph. Two architectures built from pipelined functional units are described. A prototype containing nine processing elements was fabricated in a 1.6-¿m CMOS technology

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KW - digital signal processing chips

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Jayasinghe JAKS, Jayasinghe JAKS, El Hadidy FM, El hadidy F, Karagiannis G, Herrmann OE et al. Two-Level Pipepined Systolic Array Graphics Engine. IEEE journal of solid-state circuits. 1991;26(3):229-236. https://doi.org/10.1109/4.75000