Abstract
This paper presents two soft-error mitigation methods for DSP processors. Considering that a DSP processor is composed of several functional units and each functional unit constitutes of a control unit, some registers and combinational logic, a unique characteristic of DSP workloads has been deployed to develop a masking mechanism for the control-logic of each functional unit. Combinational logic has been elaborated with a fast recovery mechanism to isolate the fault-free functional units and re-execute the erroneous instruction. These techniques have been implemented on a DSP processor in order to assess the achieved fault-tolerance versus the imposed overheads.
Original language | Undefined |
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Title of host publication | 19th IEEE European Test Symposium, ETS 2014 |
Place of Publication | USA |
Publisher | IEEE |
Pages | 1-6 |
Number of pages | 6 |
ISBN (Print) | 978-1-4799-3415-7 |
DOIs | |
Publication status | Published - May 2014 |
Event | 19th IEEE European Test Symposium, ETS 2014 - Heinz-Nixdorf Forum, Paderborn, Germany Duration: 28 May 2014 → 30 May 2014 Conference number: 19 http://www.ets14.de/ |
Publication series
Name | |
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Publisher | IEEE Computer Society |
Conference
Conference | 19th IEEE European Test Symposium, ETS 2014 |
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Abbreviated title | ETS |
Country/Territory | Germany |
City | Paderborn |
Period | 28/05/14 → 30/05/14 |
Internet address |
Keywords
- EWI-25170
- METIS-309607
- IR-92929