Two soft-error mitigation techniques for functional units of DSP processors

A. Rohani; Hans G. Kerkhoff

doi:10.1109/ETS.2014.6847792

Two soft-error mitigation techniques for functional units of DSP processors

A. Rohani, Hans G. Kerkhoff

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Abstract

This paper presents two soft-error mitigation methods for DSP processors. Considering that a DSP processor is composed of several functional units and each functional unit constitutes of a control unit, some registers and combinational logic, a unique characteristic of DSP workloads has been deployed to develop a masking mechanism for the control-logic of each functional unit. Combinational logic has been elaborated with a fast recovery mechanism to isolate the fault-free functional units and re-execute the erroneous instruction. These techniques have been implemented on a DSP processor in order to assess the achieved fault-tolerance versus the imposed overheads.

Original language	Undefined
Title of host publication	19th IEEE European Test Symposium, ETS 2014
Place of Publication	USA
Publisher	IEEE
Pages	1-6
Number of pages	6
ISBN (Print)	978-1-4799-3415-7
DOIs	https://doi.org/10.1109/ETS.2014.6847792
Publication status	Published - May 2014
Event	19th IEEE European Test Symposium, ETS 2014 - Heinz-Nixdorf Forum, Paderborn, Germany Duration: 28 May 2014 → 30 May 2014 Conference number: 19 http://www.ets14.de/

Publication series

Name
Publisher	IEEE Computer Society

Conference

Conference	19th IEEE European Test Symposium, ETS 2014
Abbreviated title	ETS
Country/Territory	Germany
City	Paderborn
Period	28/05/14 → 30/05/14
Internet address	http://www.ets14.de/

Keywords

EWI-25170
METIS-309607
IR-92929

Access to Document

10.1109/ETS.2014.6847792

http://eprints.eemcs.utwente.nl/secure2/25170/01/06847792.pdf

Cite this

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title = "Two soft-error mitigation techniques for functional units of DSP processors",

abstract = "This paper presents two soft-error mitigation methods for DSP processors. Considering that a DSP processor is composed of several functional units and each functional unit constitutes of a control unit, some registers and combinational logic, a unique characteristic of DSP workloads has been deployed to develop a masking mechanism for the control-logic of each functional unit. Combinational logic has been elaborated with a fast recovery mechanism to isolate the fault-free functional units and re-execute the erroneous instruction. These techniques have been implemented on a DSP processor in order to assess the achieved fault-tolerance versus the imposed overheads.",

keywords = "EWI-25170, METIS-309607, IR-92929",

author = "A. Rohani and Kerkhoff, {Hans G.}",

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doi = "10.1109/ETS.2014.6847792",

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AU - Kerkhoff, Hans G.

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PY - 2014/5

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N2 - This paper presents two soft-error mitigation methods for DSP processors. Considering that a DSP processor is composed of several functional units and each functional unit constitutes of a control unit, some registers and combinational logic, a unique characteristic of DSP workloads has been deployed to develop a masking mechanism for the control-logic of each functional unit. Combinational logic has been elaborated with a fast recovery mechanism to isolate the fault-free functional units and re-execute the erroneous instruction. These techniques have been implemented on a DSP processor in order to assess the achieved fault-tolerance versus the imposed overheads.

AB - This paper presents two soft-error mitigation methods for DSP processors. Considering that a DSP processor is composed of several functional units and each functional unit constitutes of a control unit, some registers and combinational logic, a unique characteristic of DSP workloads has been deployed to develop a masking mechanism for the control-logic of each functional unit. Combinational logic has been elaborated with a fast recovery mechanism to isolate the fault-free functional units and re-execute the erroneous instruction. These techniques have been implemented on a DSP processor in order to assess the achieved fault-tolerance versus the imposed overheads.

KW - EWI-25170

KW - METIS-309607

KW - IR-92929

U2 - 10.1109/ETS.2014.6847792

DO - 10.1109/ETS.2014.6847792

M3 - Conference contribution

SN - 978-1-4799-3415-7

SP - 1

EP - 6

BT - 19th IEEE European Test Symposium, ETS 2014

PB - IEEE

CY - USA

T2 - 19th IEEE European Test Symposium, ETS 2014

Y2 - 28 May 2014 through 30 May 2014

ER -