Two soft-error mitigation techniques for functional units of DSP processors

A. Rohani, Hans G. Kerkhoff

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review


    This paper presents two soft-error mitigation methods for DSP processors. Considering that a DSP processor is composed of several functional units and each functional unit constitutes of a control unit, some registers and combinational logic, a unique characteristic of DSP workloads has been deployed to develop a masking mechanism for the control-logic of each functional unit. Combinational logic has been elaborated with a fast recovery mechanism to isolate the fault-free functional units and re-execute the erroneous instruction. These techniques have been implemented on a DSP processor in order to assess the achieved fault-tolerance versus the imposed overheads.
    Original languageUndefined
    Title of host publication19th IEEE European Test Symposium, ETS 2014
    Place of PublicationUSA
    PublisherIEEE Computer Society
    Number of pages6
    ISBN (Print)978-1-4799-3415-7
    Publication statusPublished - May 2014
    Event19th IEEE European Test Symposium, ETS 2014 - Heinz-Nixdorf Forum, Paderborn, Germany
    Duration: 28 May 201430 May 2014
    Conference number: 19

    Publication series

    PublisherIEEE Computer Society


    Conference19th IEEE European Test Symposium, ETS 2014
    Abbreviated titleETS
    Internet address


    • EWI-25170
    • METIS-309607
    • IR-92929

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