Ultra-Low Voltage 4-to-2 Compressors for Near-Vth Computing

Anuradha C. Ranasinghe; Sabih H. Gerez

doi:10.1109/ISCAS45731.2020.9181126

Ultra-Low Voltage 4-to-2 Compressors for Near-Vth Computing

Anuradha C. Ranasinghe^*, Sabih H. Gerez

^*Corresponding author for this work

Computer Architecture Design and Test for Embedded Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

28 Downloads (Pure)

Abstract

This paper presents two novel circuit arrangements for an ultra-low voltage, low-power 4-to-2 compressor targeting typical near-V th application domain. A hybrid logic style is utilized to exploit energy efficiency by means of parasitic reduction in circuit blocks. Proposed structures are evaluated against prevalent compressors in terms of their typical figure of merits and noise immunity. From extensive post-layout simulations in 65-nm bulk CMOS process technology, the most optimal arrangement was found to be 35% more power efficient, 3.4% faster, 8% more area efficient and 37% better in PDP at 0.4V DD compared to most appealing implementations in literature.

Original language	English
Title of host publication	IEEE International Symposium on Circuits and Systems (ISCAS)
Publisher	IEEE
Number of pages	5
ISBN (Electronic)	978-1-7281-3320-1
ISBN (Print)	978-1-7281-3321-8
DOIs	https://doi.org/10.1109/ISCAS45731.2020.9181126
Publication status	Published - 2020
Event	52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Virtual Conference, Virtual, Online, Spain Duration: 10 Oct 2020 → 21 Oct 2020 Conference number: 52 https://www.iscas2020.org/

Conference

Conference	52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020
Abbreviated title	ISCAS 2020
Country/Territory	Spain
City	Virtual, Online
Period	10/10/20 → 21/10/20
Internet address	https://www.iscas2020.org/

Keywords

22/2 OA procedure

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/ISCAS45731.2020.9181126

Ranasinghe-2020-Ultra-low-voltage--to--compressors-Final published version, 239 KBLicence: Taverne

Cite this

@inproceedings{9436525199fe460eaac6478be4cc741f,

title = "Ultra-Low Voltage 4-to-2 Compressors for Near-Vth Computing",

abstract = "This paper presents two novel circuit arrangements for an ultra-low voltage, low-power 4-to-2 compressor targeting typical near-V th application domain. A hybrid logic style is utilized to exploit energy efficiency by means of parasitic reduction in circuit blocks. Proposed structures are evaluated against prevalent compressors in terms of their typical figure of merits and noise immunity. From extensive post-layout simulations in 65-nm bulk CMOS process technology, the most optimal arrangement was found to be 35% more power efficient, 3.4% faster, 8% more area efficient and 37% better in PDP at 0.4V DD compared to most appealing implementations in literature.",

keywords = "22/2 OA procedure",

author = "Ranasinghe, {Anuradha C.} and Gerez, {Sabih H.}",

year = "2020",

doi = "10.1109/ISCAS45731.2020.9181126",

language = "English",

isbn = "978-1-7281-3321-8",

booktitle = "IEEE International Symposium on Circuits and Systems (ISCAS)",

publisher = "IEEE",

address = "United States",

note = "52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020, ISCAS 2020 ; Conference date: 10-10-2020 Through 21-10-2020",

url = "https://www.iscas2020.org/",

}

TY - GEN

T1 - Ultra-Low Voltage 4-to-2 Compressors for Near-Vth Computing

AU - Ranasinghe, Anuradha C.

AU - Gerez, Sabih H.

N1 - Conference code: 52

PY - 2020

Y1 - 2020

N2 - This paper presents two novel circuit arrangements for an ultra-low voltage, low-power 4-to-2 compressor targeting typical near-V th application domain. A hybrid logic style is utilized to exploit energy efficiency by means of parasitic reduction in circuit blocks. Proposed structures are evaluated against prevalent compressors in terms of their typical figure of merits and noise immunity. From extensive post-layout simulations in 65-nm bulk CMOS process technology, the most optimal arrangement was found to be 35% more power efficient, 3.4% faster, 8% more area efficient and 37% better in PDP at 0.4V DD compared to most appealing implementations in literature.

AB - This paper presents two novel circuit arrangements for an ultra-low voltage, low-power 4-to-2 compressor targeting typical near-V th application domain. A hybrid logic style is utilized to exploit energy efficiency by means of parasitic reduction in circuit blocks. Proposed structures are evaluated against prevalent compressors in terms of their typical figure of merits and noise immunity. From extensive post-layout simulations in 65-nm bulk CMOS process technology, the most optimal arrangement was found to be 35% more power efficient, 3.4% faster, 8% more area efficient and 37% better in PDP at 0.4V DD compared to most appealing implementations in literature.

KW - 22/2 OA procedure

U2 - 10.1109/ISCAS45731.2020.9181126

DO - 10.1109/ISCAS45731.2020.9181126

M3 - Conference contribution

SN - 978-1-7281-3321-8

BT - IEEE International Symposium on Circuits and Systems (ISCAS)

PB - IEEE

T2 - 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020

Y2 - 10 October 2020 through 21 October 2020

ER -