This paper presents two novel circuit arrangements for an ultra-low voltage, low-power 4-to-2 compressor targeting typical near-V th application domain. A hybrid logic style is utilized to exploit energy efficiency by means of parasitic reduction in circuit blocks. Proposed structures are evaluated against prevalent compressors in terms of their typical figure of merits and noise immunity. From extensive post-layout simulations in 65-nm bulk CMOS process technology, the most optimal arrangement was found to be 35% more power efficient, 3.4% faster, 8% more area efficient and 37% better in PDP at 0.4V DD compared to most appealing implementations in literature.
|Title of host publication||IEEE International Symposium on Circuits and Systems (ISCAS)|
|Number of pages||5|
|Publication status||Published - 2020|
|Event||IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Virtual Conference, Sevilla, Spain|
Duration: 10 Oct 2020 → 21 Oct 2020
|Conference||IEEE International Symposium on Circuits and Systems, ISCAS 2020|
|Period||10/10/20 → 21/10/20|