Unifying partitioning and placement for SAT-based exploration of heterogeneous reconfigurable SOCS

Stefan Wildermann, Jürgen Teich, Daniel Ziener

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

4 Citations (Scopus)

Abstract

Heterogeneous reconfigurable SoCs provide more flexibility, maintainability, and re-usability than hardwired SoCs. Designing such systems is a complex task, since early decisions, as design partitioning, influence the subsequent design steps, such as placement of partially reconfigurable modules In this paper, we investigate a symbolic design space exploration (DSE) approach for this kind of SoCs, where we transform the problem of finding a feasible implementation to a Boolean satisfiability problem (SAT). We present three encoding variants which unify partitioning and placement to overcome the drawbacks of their separation. In particular, we will show that the runtime of DSE can be speeded up when we perform a preprocessing mechansim that identifies those partitionings which inevitably lead to infeasibility, and then incorporate this information into the symbolic encoding for calculating feasible placements. Our experiments show the effectiveness of our SAT-based approach and compare the presented encoding variants.

Original languageEnglish
Title of host publication2011 21st International Conference on Field Programmable Logic and Applications
Pages429-434
Number of pages6
DOIs
Publication statusPublished - 2011
Externally publishedYes

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Wildermann, S., Teich, J., & Ziener, D. (2011). Unifying partitioning and placement for SAT-based exploration of heterogeneous reconfigurable SOCS. In 2011 21st International Conference on Field Programmable Logic and Applications (pp. 429-434). [6044858] https://doi.org/10.1109/FPL.2011.85
Wildermann, Stefan ; Teich, Jürgen ; Ziener, Daniel. / Unifying partitioning and placement for SAT-based exploration of heterogeneous reconfigurable SOCS. 2011 21st International Conference on Field Programmable Logic and Applications. 2011. pp. 429-434
@inproceedings{fa94d8e2973e41098830f4dc42501a02,
title = "Unifying partitioning and placement for SAT-based exploration of heterogeneous reconfigurable SOCS",
abstract = "Heterogeneous reconfigurable SoCs provide more flexibility, maintainability, and re-usability than hardwired SoCs. Designing such systems is a complex task, since early decisions, as design partitioning, influence the subsequent design steps, such as placement of partially reconfigurable modules In this paper, we investigate a symbolic design space exploration (DSE) approach for this kind of SoCs, where we transform the problem of finding a feasible implementation to a Boolean satisfiability problem (SAT). We present three encoding variants which unify partitioning and placement to overcome the drawbacks of their separation. In particular, we will show that the runtime of DSE can be speeded up when we perform a preprocessing mechansim that identifies those partitionings which inevitably lead to infeasibility, and then incorporate this information into the symbolic encoding for calculating feasible placements. Our experiments show the effectiveness of our SAT-based approach and compare the presented encoding variants.",
author = "Stefan Wildermann and J{\"u}rgen Teich and Daniel Ziener",
year = "2011",
doi = "10.1109/FPL.2011.85",
language = "English",
isbn = "9780769545295",
pages = "429--434",
booktitle = "2011 21st International Conference on Field Programmable Logic and Applications",

}

Wildermann, S, Teich, J & Ziener, D 2011, Unifying partitioning and placement for SAT-based exploration of heterogeneous reconfigurable SOCS. in 2011 21st International Conference on Field Programmable Logic and Applications., 6044858, pp. 429-434. https://doi.org/10.1109/FPL.2011.85

Unifying partitioning and placement for SAT-based exploration of heterogeneous reconfigurable SOCS. / Wildermann, Stefan; Teich, Jürgen; Ziener, Daniel.

2011 21st International Conference on Field Programmable Logic and Applications. 2011. p. 429-434 6044858.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

TY - GEN

T1 - Unifying partitioning and placement for SAT-based exploration of heterogeneous reconfigurable SOCS

AU - Wildermann, Stefan

AU - Teich, Jürgen

AU - Ziener, Daniel

PY - 2011

Y1 - 2011

N2 - Heterogeneous reconfigurable SoCs provide more flexibility, maintainability, and re-usability than hardwired SoCs. Designing such systems is a complex task, since early decisions, as design partitioning, influence the subsequent design steps, such as placement of partially reconfigurable modules In this paper, we investigate a symbolic design space exploration (DSE) approach for this kind of SoCs, where we transform the problem of finding a feasible implementation to a Boolean satisfiability problem (SAT). We present three encoding variants which unify partitioning and placement to overcome the drawbacks of their separation. In particular, we will show that the runtime of DSE can be speeded up when we perform a preprocessing mechansim that identifies those partitionings which inevitably lead to infeasibility, and then incorporate this information into the symbolic encoding for calculating feasible placements. Our experiments show the effectiveness of our SAT-based approach and compare the presented encoding variants.

AB - Heterogeneous reconfigurable SoCs provide more flexibility, maintainability, and re-usability than hardwired SoCs. Designing such systems is a complex task, since early decisions, as design partitioning, influence the subsequent design steps, such as placement of partially reconfigurable modules In this paper, we investigate a symbolic design space exploration (DSE) approach for this kind of SoCs, where we transform the problem of finding a feasible implementation to a Boolean satisfiability problem (SAT). We present three encoding variants which unify partitioning and placement to overcome the drawbacks of their separation. In particular, we will show that the runtime of DSE can be speeded up when we perform a preprocessing mechansim that identifies those partitionings which inevitably lead to infeasibility, and then incorporate this information into the symbolic encoding for calculating feasible placements. Our experiments show the effectiveness of our SAT-based approach and compare the presented encoding variants.

UR - http://www.scopus.com/inward/record.url?scp=80455129779&partnerID=8YFLogxK

U2 - 10.1109/FPL.2011.85

DO - 10.1109/FPL.2011.85

M3 - Conference contribution

SN - 9780769545295

SP - 429

EP - 434

BT - 2011 21st International Conference on Field Programmable Logic and Applications

ER -

Wildermann S, Teich J, Ziener D. Unifying partitioning and placement for SAT-based exploration of heterogeneous reconfigurable SOCS. In 2011 21st International Conference on Field Programmable Logic and Applications. 2011. p. 429-434. 6044858 https://doi.org/10.1109/FPL.2011.85