Unifying partitioning and placement for SAT-based exploration of heterogeneous reconfigurable SOCS

Stefan Wildermann*, Jürgen Teich, Daniel Ziener

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

4 Citations (Scopus)

Abstract

Heterogeneous reconfigurable SoCs provide more flexibility, maintainability, and re-usability than hardwired SoCs. Designing such systems is a complex task, since early decisions, as design partitioning, influence the subsequent design steps, such as placement of partially reconfigurable modules In this paper, we investigate a symbolic design space exploration (DSE) approach for this kind of SoCs, where we transform the problem of finding a feasible implementation to a Boolean satisfiability problem (SAT). We present three encoding variants which unify partitioning and placement to overcome the drawbacks of their separation. In particular, we will show that the runtime of DSE can be speeded up when we perform a preprocessing mechansim that identifies those partitionings which inevitably lead to infeasibility, and then incorporate this information into the symbolic encoding for calculating feasible placements. Our experiments show the effectiveness of our SAT-based approach and compare the presented encoding variants.

Original languageEnglish
Title of host publication2011 21st International Conference on Field Programmable Logic and Applications
Pages429-434
Number of pages6
DOIs
Publication statusPublished - 2011
Externally publishedYes

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    Wildermann, S., Teich, J., & Ziener, D. (2011). Unifying partitioning and placement for SAT-based exploration of heterogeneous reconfigurable SOCS. In 2011 21st International Conference on Field Programmable Logic and Applications (pp. 429-434). [6044858] https://doi.org/10.1109/FPL.2011.85