Using a Pulsed Supply Voltage for Delay Faults Testing of Digital Circuits in a Digital Oscillation Environment

H.J. Vermaak, Hans G. Kerkhoff, G.D. Jordaan

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    Abstract

    High-performance digital circuits with aggressive timing constraints are usually very susceptible to delay faults. Much research done on delay fault detection needs a rather complicated test setup together with precise test clock requirements. In this paper, we propose a test technique based on the digital oscillation test method. The technique, which was simulated in software, consists of sensitizing a critical path in the digital circuit under test and incorporating the path into an oscillation ring. The supply voltage to the oscillation ring is then varied to detect delay and stuck-at faults in the path.
    Original languageUndefined
    Title of host publicationProceedings AFRICON
    Place of PublicationGeorge, South Africa
    PublisherIEEE
    Pages47-52
    Number of pages6
    ISBN (Print)0-7803-7570-X
    DOIs
    Publication statusPublished - 2 Oct 2002
    Event6th IEEE Africon Conference in Africa, AFRICON 2002 - George, South Africa
    Duration: 2 Oct 20024 Oct 2002

    Publication series

    Name
    PublisherIEEE
    Volume1

    Other

    Other6th IEEE Africon Conference in Africa, AFRICON 2002
    Period2/10/024/10/02
    Other2-4 Oct. 2002

    Keywords

    • METIS-207863
    • IR-43949

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