Using a Pulsed Supply Voltage for Delay Faults Testing of Digital Circuits in a Digital Oscillation Environment

H.J. Vermaak; H.G. Kerkhoff; G.D. Jordaan

doi:10.1109/AFRCON.2002.1146804

Using a Pulsed Supply Voltage for Delay Faults Testing of Digital Circuits in a Digital Oscillation Environment

H.J. Vermaak
, H.G. Kerkhoff
, G.D. Jordaan

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

High-performance digital circuits with aggressive timing constraints are usually very susceptible to delay faults. Much research done on delay fault detection needs a rather complicated test setup together with precise test clock requirements. In this paper, we propose a test technique based on the digital oscillation test method. The technique, which was simulated in software, consists of sensitizing a critical path in the digital circuit under test and incorporating the path into an oscillation ring. The supply voltage to the oscillation ring is then varied to detect delay and stuck-at faults in the path.

Original language	English
Title of host publication	Proceedings 6th AFRICON Conference 2002
Place of Publication	Piscataway, NJ
Publisher	IEEE
Pages	47-52
Number of pages	6
Volume	1
ISBN (Print)	0-7803-7570-X
DOIs	https://doi.org/10.1109/AFRCON.2002.1146804
Publication status	Published - 2 Oct 2002
Event	6th IEEE Africon Conference in Africa, AFRICON 2002 - George, South Africa Duration: 2 Oct 2002 → 4 Oct 2002 Conference number: 6

Other

Other	6th IEEE Africon Conference in Africa, AFRICON 2002
Abbreviated title	AFRICON
Country/Territory	South Africa
City	George
Period	2/10/02 → 4/10/02

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10.1109/AFRCON.2002.1146804

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@inproceedings{b1bdc4266042417d9b251603d11e9161,

title = "Using a Pulsed Supply Voltage for Delay Faults Testing of Digital Circuits in a Digital Oscillation Environment",

abstract = "High-performance digital circuits with aggressive timing constraints are usually very susceptible to delay faults. Much research done on delay fault detection needs a rather complicated test setup together with precise test clock requirements. In this paper, we propose a test technique based on the digital oscillation test method. The technique, which was simulated in software, consists of sensitizing a critical path in the digital circuit under test and incorporating the path into an oscillation ring. The supply voltage to the oscillation ring is then varied to detect delay and stuck-at faults in the path.",

author = "H.J. Vermaak and H.G. Kerkhoff and G.D. Jordaan",

year = "2002",

month = oct,

day = "2",

doi = "10.1109/AFRCON.2002.1146804",

language = "English",

isbn = "0-7803-7570-X",

volume = "1",

pages = "47--52",

booktitle = "Proceedings 6th AFRICON Conference 2002",

publisher = "IEEE",

address = "United States",

note = "6th IEEE Africon Conference in Africa, AFRICON 2002, AFRICON ; Conference date: 02-10-2002 Through 04-10-2002",

}

Vermaak, HJ, Kerkhoff, HG & Jordaan, GD 2002, Using a Pulsed Supply Voltage for Delay Faults Testing of Digital Circuits in a Digital Oscillation Environment. in Proceedings 6th AFRICON Conference 2002. vol. 1, IEEE, Piscataway, NJ, pp. 47-52, 6th IEEE Africon Conference in Africa, AFRICON 2002, George, South Africa, 2/10/02. https://doi.org/10.1109/AFRCON.2002.1146804

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T1 - Using a Pulsed Supply Voltage for Delay Faults Testing of Digital Circuits in a Digital Oscillation Environment

AU - Vermaak, H.J.

AU - Kerkhoff, H.G.

AU - Jordaan, G.D.

N1 - Conference code: 6

PY - 2002/10/2

Y1 - 2002/10/2

N2 - High-performance digital circuits with aggressive timing constraints are usually very susceptible to delay faults. Much research done on delay fault detection needs a rather complicated test setup together with precise test clock requirements. In this paper, we propose a test technique based on the digital oscillation test method. The technique, which was simulated in software, consists of sensitizing a critical path in the digital circuit under test and incorporating the path into an oscillation ring. The supply voltage to the oscillation ring is then varied to detect delay and stuck-at faults in the path.

AB - High-performance digital circuits with aggressive timing constraints are usually very susceptible to delay faults. Much research done on delay fault detection needs a rather complicated test setup together with precise test clock requirements. In this paper, we propose a test technique based on the digital oscillation test method. The technique, which was simulated in software, consists of sensitizing a critical path in the digital circuit under test and incorporating the path into an oscillation ring. The supply voltage to the oscillation ring is then varied to detect delay and stuck-at faults in the path.

U2 - 10.1109/AFRCON.2002.1146804

DO - 10.1109/AFRCON.2002.1146804

M3 - Conference contribution

SN - 0-7803-7570-X

VL - 1

SP - 47

EP - 52

BT - Proceedings 6th AFRICON Conference 2002

PB - IEEE

CY - Piscataway, NJ

T2 - 6th IEEE Africon Conference in Africa, AFRICON 2002

Y2 - 2 October 2002 through 4 October 2002

ER -

Using a Pulsed Supply Voltage for Delay Faults Testing of Digital Circuits in a Digital Oscillation Environment

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