Using an FPGA for Fast Bit Accurate SoC Simulation

P.T. Wolkotte; P.K.F. Holzenspies; Gerardus Johannes Maria Smit

doi:10.1109/IPDPS.2007.370374

Using an FPGA for Fast Bit Accurate SoC Simulation

P.T. Wolkotte, P.K.F. Holzenspies, Gerardus Johannes Maria Smit

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

4 Citations (Scopus)

62 Downloads (Pure)

Abstract

In this paper we describe a sequential simulation method to simulate large parallel homo- and heterogeneous systems on a single FPGA. The method is applicable for parallel systems were lengthy cycle and bit accurate simulations are required. It is particularly designed for systems that do not fit completely on the simulation platform (i.e. FPGA). As a case study, we use a Network-on-Chip (NoC) that is simulated in SystemC and on the described FPGA simulator. This enables us to observe the NoC behavior under a large variety of traffic patterns. Compared with the SystemC simulation we achieved a factor 80-300 of speed improvement, without compromising the cycle and bit level accuracy.

Original language	English
Title of host publication	Proceedings of the 21th IEEE International Parallel and Distributed Processing Symposium (IPDPS'07)
Place of Publication	Piscataway
Publisher	IEEE
Pages	167
Number of pages	8
ISBN (Print)	1-4244-0910-1
DOIs	https://doi.org/10.1109/IPDPS.2007.370374
Publication status	Published - Mar 2007
Event	14th Reconfigurable Architectures Workshop, RAW 2007 - Long Beach, United States Duration: 26 Mar 2006 → 27 Mar 2006 Conference number: 14

Publication series

Name
Publisher	IEEE Computer Society Press
Number	07TH8938

Workshop

Workshop	14th Reconfigurable Architectures Workshop, RAW 2007
Abbreviated title	RAW
Country/Territory	United States
City	Long Beach
Period	26/03/06 → 27/03/06

Keywords

EWI-9680
EC Grant Agreement nr.: FP6/001908
IR-67065
METIS-242165
CAES-EEA: Efficient Embedded Architectures

Access to Document

10.1109/IPDPS.2007.370374

RAW-40-paper-1

Cite this

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title = "Using an FPGA for Fast Bit Accurate SoC Simulation",

abstract = "In this paper we describe a sequential simulation method to simulate large parallel homo- and heterogeneous systems on a single FPGA. The method is applicable for parallel systems were lengthy cycle and bit accurate simulations are required. It is particularly designed for systems that do not fit completely on the simulation platform (i.e. FPGA). As a case study, we use a Network-on-Chip (NoC) that is simulated in SystemC and on the described FPGA simulator. This enables us to observe the NoC behavior under a large variety of traffic patterns. Compared with the SystemC simulation we achieved a factor 80-300 of speed improvement, without compromising the cycle and bit level accuracy.",

keywords = "EWI-9680, EC Grant Agreement nr.: FP6/001908, IR-67065, METIS-242165, CAES-EEA: Efficient Embedded Architectures",

author = "P.T. Wolkotte and P.K.F. Holzenspies and Smit, {Gerardus Johannes Maria}",

year = "2007",

month = mar,

doi = "10.1109/IPDPS.2007.370374",

language = "English",

isbn = "1-4244-0910-1",

publisher = "IEEE",

number = "07TH8938",

pages = "167",

booktitle = "Proceedings of the 21th IEEE International Parallel and Distributed Processing Symposium (IPDPS'07)",

address = "United States",

note = "14th Reconfigurable Architectures Workshop, RAW 2007, RAW ; Conference date: 26-03-2006 Through 27-03-2006",

}

Wolkotte, PT, Holzenspies, PKF & Smit, GJM 2007, Using an FPGA for Fast Bit Accurate SoC Simulation. in Proceedings of the 21th IEEE International Parallel and Distributed Processing Symposium (IPDPS'07). IEEE, Piscataway, pp. 167, 14th Reconfigurable Architectures Workshop, RAW 2007, Long Beach, California, United States, 26/03/06. https://doi.org/10.1109/IPDPS.2007.370374

Using an FPGA for Fast Bit Accurate SoC Simulation. / Wolkotte, P.T.; Holzenspies, P.K.F.; Smit, Gerardus Johannes Maria.
Proceedings of the 21th IEEE International Parallel and Distributed Processing Symposium (IPDPS'07). Piscataway: IEEE, 2007. p. 167.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Using an FPGA for Fast Bit Accurate SoC Simulation

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AU - Holzenspies, P.K.F.

AU - Smit, Gerardus Johannes Maria

N1 - Conference code: 14

PY - 2007/3

Y1 - 2007/3

N2 - In this paper we describe a sequential simulation method to simulate large parallel homo- and heterogeneous systems on a single FPGA. The method is applicable for parallel systems were lengthy cycle and bit accurate simulations are required. It is particularly designed for systems that do not fit completely on the simulation platform (i.e. FPGA). As a case study, we use a Network-on-Chip (NoC) that is simulated in SystemC and on the described FPGA simulator. This enables us to observe the NoC behavior under a large variety of traffic patterns. Compared with the SystemC simulation we achieved a factor 80-300 of speed improvement, without compromising the cycle and bit level accuracy.

AB - In this paper we describe a sequential simulation method to simulate large parallel homo- and heterogeneous systems on a single FPGA. The method is applicable for parallel systems were lengthy cycle and bit accurate simulations are required. It is particularly designed for systems that do not fit completely on the simulation platform (i.e. FPGA). As a case study, we use a Network-on-Chip (NoC) that is simulated in SystemC and on the described FPGA simulator. This enables us to observe the NoC behavior under a large variety of traffic patterns. Compared with the SystemC simulation we achieved a factor 80-300 of speed improvement, without compromising the cycle and bit level accuracy.

KW - EWI-9680

KW - EC Grant Agreement nr.: FP6/001908

KW - IR-67065

KW - METIS-242165

KW - CAES-EEA: Efficient Embedded Architectures

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DO - 10.1109/IPDPS.2007.370374

M3 - Conference contribution

SN - 1-4244-0910-1

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BT - Proceedings of the 21th IEEE International Parallel and Distributed Processing Symposium (IPDPS'07)

PB - IEEE

CY - Piscataway

T2 - 14th Reconfigurable Architectures Workshop, RAW 2007

Y2 - 26 March 2006 through 27 March 2006

ER -

Using an FPGA for Fast Bit Accurate SoC Simulation

Abstract

Publication series

Workshop

Keywords

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Cite this