Using an FPGA for Fast Bit Accurate SoC Simulation

P.T. Wolkotte, P.K.F. Holzenspies, Gerardus Johannes Maria Smit

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    4 Citations (Scopus)
    44 Downloads (Pure)


    In this paper we describe a sequential simulation method to simulate large parallel homo- and heterogeneous systems on a single FPGA. The method is applicable for parallel systems were lengthy cycle and bit accurate simulations are required. It is particularly designed for systems that do not fit completely on the simulation platform (i.e. FPGA). As a case study, we use a Network-on-Chip (NoC) that is simulated in SystemC and on the described FPGA simulator. This enables us to observe the NoC behavior under a large variety of traffic patterns. Compared with the SystemC simulation we achieved a factor 80-300 of speed improvement, without compromising the cycle and bit level accuracy.
    Original languageEnglish
    Title of host publicationProceedings of the 21th IEEE International Parallel and Distributed Processing Symposium (IPDPS'07)
    Place of PublicationPiscataway
    Number of pages8
    ISBN (Print)1-4244-0910-1
    Publication statusPublished - Mar 2007
    Event14th Reconfigurable Architectures Workshop, RAW 2007 - Long Beach, United States
    Duration: 26 Mar 200627 Mar 2006
    Conference number: 14

    Publication series

    PublisherIEEE Computer Society Press


    Workshop14th Reconfigurable Architectures Workshop, RAW 2007
    Abbreviated titleRAW
    Country/TerritoryUnited States
    CityLong Beach


    • EWI-9680
    • EC Grant Agreement nr.: FP6/001908
    • IR-67065
    • METIS-242165
    • CAES-EEA: Efficient Embedded Architectures

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