Using an FPGA for Fast Bit Accurate SoC Simulation

P.T. Wolkotte, P.K.F. Holzenspies, Gerardus Johannes Maria Smit

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

3 Citations (Scopus)
11 Downloads (Pure)

Abstract

In this paper we describe a sequential simulation method to simulate large parallel homo- and heterogeneous systems on a single FPGA. The method is applicable for parallel systems were lengthy cycle and bit accurate simulations are required. It is particularly designed for systems that do not fit completely on the simulation platform (i.e. FPGA). As a case study, we use a Network-on-Chip (NoC) that is simulated in SystemC and on the described FPGA simulator. This enables us to observe the NoC behavior under a large variety of traffic patterns. Compared with the SystemC simulation we achieved a factor 80-300 of speed improvement, without compromising the cycle and bit level accuracy.
Original languageEnglish
Title of host publicationProceedings of the 21th IEEE International Parallel and Distributed Processing Symposium (IPDPS'07)
Place of PublicationPiscataway
PublisherIEEE Computer Society
Pages167
Number of pages8
ISBN (Print)1-4244-0910-1
DOIs
Publication statusPublished - Mar 2007
Event14th Reconfigurable Architectures Workshop, RAW 2007 - Long Beach, United States
Duration: 26 Mar 200627 Mar 2006
Conference number: 14

Publication series

Name
PublisherIEEE Computer Society Press
Number07TH8938

Workshop

Workshop14th Reconfigurable Architectures Workshop, RAW 2007
Abbreviated titleRAW
CountryUnited States
CityLong Beach
Period26/03/0627/03/06

Fingerprint

Field programmable gate arrays (FPGA)
Simulators
System-on-chip
Network-on-chip

Keywords

  • EWI-9680
  • EC Grant Agreement nr.: FP6/001908
  • IR-67065
  • METIS-242165
  • CAES-EEA: Efficient Embedded Architectures

Cite this

Wolkotte, P. T., Holzenspies, P. K. F., & Smit, G. J. M. (2007). Using an FPGA for Fast Bit Accurate SoC Simulation. In Proceedings of the 21th IEEE International Parallel and Distributed Processing Symposium (IPDPS'07) (pp. 167). Piscataway: IEEE Computer Society. https://doi.org/10.1109/IPDPS.2007.370374
Wolkotte, P.T. ; Holzenspies, P.K.F. ; Smit, Gerardus Johannes Maria. / Using an FPGA for Fast Bit Accurate SoC Simulation. Proceedings of the 21th IEEE International Parallel and Distributed Processing Symposium (IPDPS'07). Piscataway : IEEE Computer Society, 2007. pp. 167
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Wolkotte, PT, Holzenspies, PKF & Smit, GJM 2007, Using an FPGA for Fast Bit Accurate SoC Simulation. in Proceedings of the 21th IEEE International Parallel and Distributed Processing Symposium (IPDPS'07). IEEE Computer Society, Piscataway, pp. 167, 14th Reconfigurable Architectures Workshop, RAW 2007, Long Beach, United States, 26/03/06. https://doi.org/10.1109/IPDPS.2007.370374

Using an FPGA for Fast Bit Accurate SoC Simulation. / Wolkotte, P.T.; Holzenspies, P.K.F.; Smit, Gerardus Johannes Maria.

Proceedings of the 21th IEEE International Parallel and Distributed Processing Symposium (IPDPS'07). Piscataway : IEEE Computer Society, 2007. p. 167.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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Wolkotte PT, Holzenspies PKF, Smit GJM. Using an FPGA for Fast Bit Accurate SoC Simulation. In Proceedings of the 21th IEEE International Parallel and Distributed Processing Symposium (IPDPS'07). Piscataway: IEEE Computer Society. 2007. p. 167 https://doi.org/10.1109/IPDPS.2007.370374