Abstract
Continual advances In the manufacturing processes of integrated circuits provide designers the ability to create more complex and denser architectures and increased functionality on a single chip. The increased usage of embedded cores necessitates a core-based test strategy in which cores are also tested separately. The IEEE P1500 proposed standard for embedded core test (SECT) is a standard under development which aim is to improve the testing of core-based system chips. This paper deals with the enhancement of the test wrapper and wrapper cells to provide a structure to be able to test embedded cores for delay faults. This approach allows delay fault testing of cores by using the digital oscillation test method and the help of the enhanced elements while staying compliant to the PI500 standard.
| Original language | English |
|---|---|
| Title of host publication | IEEE AFRICON International Conferences on Electrical, Electronic and IT research activities |
| Place of Publication | Gabarone, Botswana |
| Publisher | IEEE |
| Pages | 1105-1110 |
| Number of pages | 6 |
| Volume | 2 |
| ISBN (Print) | 0-7803-8605-16 |
| DOIs | |
| Publication status | Published - 15 Sept 2004 |
| Event | 7th IEEE AFRICON International Conferences on Electrical, Electronic and IT Research Activities 2004 - Gabarone, Botswana Duration: 15 Sept 2004 → 17 Sept 2004 |
Conference
| Conference | 7th IEEE AFRICON International Conferences on Electrical, Electronic and IT Research Activities 2004 |
|---|---|
| Country/Territory | Botswana |
| City | Gabarone |
| Period | 15/09/04 → 17/09/04 |
UN SDGs
This output contributes to the following UN Sustainable Development Goals (SDGs)
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SDG 9 Industry, Innovation, and Infrastructure
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