Verifying the Authorship of Embedded IP Cores: Watermarking and Core Identification Techniques

Jürgen Teich, Daniel Ziener

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Abstract

In this paper, we present an overview of existing watermarking techniques for FPGA and ASIC designs as well as our new watermarking and identification techniques for FPGA IP cores. Unlike most existing watermarking techniques, the focus of our new techniques lies on ease of verification, even if the protected cores are embedded into a product. Moreover, we have concentrated on higher abstraction levels for embedding the watermark, particularly at the logic level, where IP cores are distributed as netlist cores. With the presented watermarking methods, it is pos-sible to watermark IP cores at the logic level and identify them with a high likelihood and in a reproducible way in a purchased product from a company that is suspected to have committed IP fraud. The investigated techniques establish the authorship by verification of either an FPGA bitfile or the power consumption of a given FPGA

Verifying the Authorship of Embedded IP Cores: Watermarking and Core Identification Techniques | Request PDF. Available from: https://www.researchgate.net/publication/266492142_Verifying_the_Authorship_of_Embedded_IP_Cores_Watermarking_and_Core_Identification_Techniques [accessed Jun 19 2018].
Original languageEnglish
Title of host publicationProceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'11)
Publication statusPublished - 1 Jul 2011
Externally publishedYes
Event11th International Conference on Engineering of Reconfigurable Systems and Algorithms 2011 - Las Vegas, United States
Duration: 18 Jul 201121 Jul 2011
Conference number: 11
https://ersaconf.org/ersa11/

Conference

Conference11th International Conference on Engineering of Reconfigurable Systems and Algorithms 2011
Abbreviated titleERSA 2011
CountryUnited States
CityLas Vegas
Period18/07/1121/07/11
Internet address

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