Vertical silicon nanowedge formation by repetitive dry and wet anisotropic etching combined with 3D self-aligned sidewall nanopatterning

Three-dimensional (3D) stacking of nano-devices is an effective method for increasing areal density, especially as downscaling of lateral device dimensions becomes impractical. This stacking is mainly achieved through plasma processing of stacked layers on top of a silicon (Si) substrate, which offers process flexibility but poses challenges in obtaining vertical sidewalls without plasma induced damage. A novel wafer-scale fabrication method is presented for realizing sub-200 nm vertically stacked Si nanowedges at the wafer scale, using iterative dry etching, wet anisotropic etching, and thermal oxidation. This approach forms nanowedges by the slow etching {111} Si planes, resulting in smooth surfaces at well-defined angles. A silicon nitride (Si3N4) hard mask is used in an iterative (etch-and-deposit) process, with its thickness determining the number of process iterations. By optimizing etch selectivity during dry etching and/or increasing the initial Si3N4 thickness, the number of process iterations can be increased. The periodicity of the nanowedges can be adjusted by varying the etch time of both dry and wet anisotropic etching. A thin silicon dioxide (SiO2) layer (∼6 nm) is grown on the nanowedges during each iteration. 3D sidewall patterning at the sub-20 nm scale is achieved using corner lithography and local oxidation of Si to selectively open the concave corners. Rhombus-shaped structures are formed at each concave corner after wet anisotropic etching of Si. This novel technology platform will allow for the 3D fabrication of high-density nanodevices for electronic, fluidic, plasmonic, and other applications.