VHDL vs. Bluespec system verilog: a case study on a Java embedded architecture

Flavius Gruian, M. Westmijze

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    12 Citations (Scopus)


    This paper compares two hardware design flows, based on the classic VHDL on one side and the relatively new Blue-spec System Verilog (BSV) on the other side. The comparison is based on a case study of a Java embedded architecture, comprising a Java native processor and a memory management unit. The processor is a micro-programmed, pipelined, Java-optimized processor (JOP), initially written in VHDL, and its BSV re-designed match BLUEJEP. Its memory management unit implements the bytecodes dealing with memory allocation, along with a mark-compact garbage collector. The two design flows are examined from several points of view, including both quantitative and qualitative measures. Based on this design experience, we conclude that the new high-abstraction level languages, such as BSV, offer in comparison to register-transfer (RT) level classic approaches roughly the same trade-offs that C++ offers vs. assembly language in the software world.
    Original languageEnglish
    Title of host publicationSAC '08
    Subtitle of host publicationThe 2008 ACM Symposium on Applied Computing, Fortaleza, Ceara, Brazil - March 16-20, 2008
    Place of PublicationNew York, NY, USA
    PublisherAssociation for Computing Machinery (ACM)
    Number of pages6
    ISBN (Print)978-1-59593-753-7
    Publication statusPublished - 2008
    Event23rd Annual ACM Symposium on Applied Computing, SAC 2008 - Fortaleza, Brazil
    Duration: 16 Mar 200820 Mar 2008
    Conference number: 23


    Conference23rd Annual ACM Symposium on Applied Computing, SAC 2008
    Abbreviated titleSAC
    Internet address


    • EWI-12984
    • METIS-263686
    • IR-62372


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