Wafer-Scale Self-Aligned Fabrication of Nanometric Curved Tunneling Junctions

Yasser Pordeli, Bjorn T.H. Borgelink, Bernhard Y. van der Wel, Erwin J.W. Berenschot, Tamer Dogan, Meint J. de Boer, Christiaan M. Bruinink, Harold J.W. Zandvliet, Han J.G.E. Gardeniers, Niels R. Tas

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

2 Citations (Scopus)
7 Downloads (Pure)

Abstract

This paper introduces a new self-aligned procedure for wafer-scale fabrication of curved metal-insulator-semiconductor (cMIS) tunneling junctions with nanometric lateral dimensions. The fabrication process is based on the use of an array of silicon nano-pillars embedded in a silicon nitride membrane. The junctions are formed at the apex of pyramidal pits and the tunneling window is defined using self-aligned corner lithography. The current densities of the functional cMIS-junctions with a 2.5 nm thick tunneling oxide layer are in the theoretically expected range.

Original languageEnglish
Title of host publication2019 20th International Conference on Solid-State Sensors, Actuators and Microsystems and Eurosensors XXXIII, TRANSDUCERS 2019 and EUROSENSORS XXXIII
Place of PublicationPiscataway, NJ
PublisherIEEE
Pages2376-2379
Number of pages4
ISBN (Electronic)9781728120072
ISBN (Print)978-1-5386-8104-6
DOIs
Publication statusPublished - Jun 2019
Event20th International Conference on Solid-State Sensors, Actuators and Microsystems (ICSSSAM) TRANSDUCERS 2019 and EUROSENSORS XXXIII - Estrel Berlin - Hotel & Congress Center, Berlin, Germany
Duration: 23 Jun 201927 Jun 2019
Conference number: 20

Conference

Conference20th International Conference on Solid-State Sensors, Actuators and Microsystems (ICSSSAM) TRANSDUCERS 2019 and EUROSENSORS XXXIII
Abbreviated titleICSSSAM
Country/TerritoryGermany
CityBerlin
Period23/06/1927/06/19

Keywords

  • corner lithography
  • geometrical asymmetry
  • MIS tunneling junction
  • silicon nanomachining

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