Abstract
This paper introduces a new self-aligned procedure for wafer-scale fabrication of curved metal-insulator-semiconductor (cMIS) tunneling junctions with nanometric lateral dimensions. The fabrication process is based on the use of an array of silicon nano-pillars embedded in a silicon nitride membrane. The junctions are formed at the apex of pyramidal pits and the tunneling window is defined using self-aligned corner lithography. The current densities of the functional cMIS-junctions with a 2.5 nm thick tunneling oxide layer are in the theoretically expected range.
Original language | English |
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Title of host publication | 2019 20th International Conference on Solid-State Sensors, Actuators and Microsystems and Eurosensors XXXIII, TRANSDUCERS 2019 and EUROSENSORS XXXIII |
Place of Publication | Piscataway, NJ |
Publisher | IEEE |
Pages | 2376-2379 |
Number of pages | 4 |
ISBN (Electronic) | 9781728120072 |
ISBN (Print) | 978-1-5386-8104-6 |
DOIs | |
Publication status | Published - Jun 2019 |
Event | 20th International Conference on Solid-State Sensors, Actuators and Microsystems (ICSSSAM) TRANSDUCERS 2019 and EUROSENSORS XXXIII - Estrel Berlin - Hotel & Congress Center, Berlin, Germany Duration: 23 Jun 2019 → 27 Jun 2019 Conference number: 20 |
Conference
Conference | 20th International Conference on Solid-State Sensors, Actuators and Microsystems (ICSSSAM) TRANSDUCERS 2019 and EUROSENSORS XXXIII |
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Abbreviated title | ICSSSAM |
Country/Territory | Germany |
City | Berlin |
Period | 23/06/19 → 27/06/19 |
Keywords
- corner lithography
- geometrical asymmetry
- MIS tunneling junction
- silicon nanomachining