A phased array antenna is a kind of antenna which is electronically reconfigurable to realize different antenna beam patterns. Delay blocks are an essential part of phased array antenna systems. Their delay-range, noise, nonlinearity, bandwidth, size, cost and power consumption have a dominant effect on the phased array antenna systems. This thesis targets CMOS implementation of delay cells suitable for compact IC implementations in standard CMOS processes, in the hundreds of MHz to low GHz range. A criterion f￪=0 has been introduced to quantify the delay vs. frequency variations in delay blocks. Mathematical formulas have been found that use f￪=0 of the delay blocks to quantify the beam direction variations in the phased array. As an approximate implementation of delay blocks, the existing gm-(R)C 1st order all-pass filters have been studied and a comparison method has been introduced to compare and benchmark them. Their circuit topologies shows that they are not directly cascade-able and have large parasitic capacitors which limit their bandwidth and are therefore unsuitable for working up to 3GHz. This has led us to the idea of a new topology for the 1st order all-pass filters. The new topology has much less parasitic components compared to other 1st order all-pass topologies, therefore it has a bandwidth up to 5x more compared to the aforementioned 1st order gm-(R)C filters. In order to demonstrate the functionality of the delay block, it has been designed and used in implementation of a 4 antenna element phased array antenna chip at 160nm technology and measurements results showed its bandwidth is wide enough to cover frequencies from 1GHz to 2.5GHz. Measurement results proved that the 1st order gm-C filters are suitable for the realization of the wideband phased array antenna system.
|Award date||26 Jun 2015|
|Place of Publication||Enschede|
|Publication status||Published - 26 Jun 2015|