Yield analysis of compiler-based arrays of embedded SRAMs

X. Wang; M. Ottavi; F. Lombardi

doi:10.1109/DFTVS.2003.1250089

Yield analysis of compiler-based arrays of embedded SRAMs

X. Wang, M. Ottavi, F. Lombardi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

7 Citations (Scopus)

Abstract

This paper presents a detailed analysis of the yield of embedded static random access memories (eSRAM) which are generated using a compiler. Defect and fault analysis inclusive of industrial data are presented for these chips by taking into account the design constructs (referred to as kernels) and the physical properties of the layout. The new tool CAYA (Compiler-based Array Yield Analysis) is based on a characterization of the design process which accounts for fault types and the relation between functional and structural faults; a novel empirical model is proposed to facilitate the yield calculation. Industrial data is provided for the analysis of various configurations with different structures and redundancy. The effectiveness and accuracy as provided by CAYA are assessed with respect to industrial designs.

Original language	English
Title of host publication	Proceedings 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Place of Publication	Piscataway, NJ
Publisher	IEEE
Number of pages	8
ISBN (Print)	0-7695-2042-1
DOIs	https://doi.org/10.1109/DFTVS.2003.1250089
Publication status	Published - 2003
Externally published	Yes

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10.1109/DFTVS.2003.1250089

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title = "Yield analysis of compiler-based arrays of embedded SRAMs",

abstract = "This paper presents a detailed analysis of the yield of embedded static random access memories (eSRAM) which are generated using a compiler. Defect and fault analysis inclusive of industrial data are presented for these chips by taking into account the design constructs (referred to as kernels) and the physical properties of the layout. The new tool CAYA (Compiler-based Array Yield Analysis) is based on a characterization of the design process which accounts for fault types and the relation between functional and structural faults; a novel empirical model is proposed to facilitate the yield calculation. Industrial data is provided for the analysis of various configurations with different structures and redundancy. The effectiveness and accuracy as provided by CAYA are assessed with respect to industrial designs.",

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AB - This paper presents a detailed analysis of the yield of embedded static random access memories (eSRAM) which are generated using a compiler. Defect and fault analysis inclusive of industrial data are presented for these chips by taking into account the design constructs (referred to as kernels) and the physical properties of the layout. The new tool CAYA (Compiler-based Array Yield Analysis) is based on a characterization of the design process which accounts for fault types and the relation between functional and structural faults; a novel empirical model is proposed to facilitate the yield calculation. Industrial data is provided for the analysis of various configurations with different structures and redundancy. The effectiveness and accuracy as provided by CAYA are assessed with respect to industrial designs.

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DO - 10.1109/DFTVS.2003.1250089

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BT - Proceedings 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

PB - IEEE

CY - Piscataway, NJ

ER -

Yield analysis of compiler-based arrays of embedded SRAMs

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