Yield analysis of compiler-based arrays of embedded SRAMs

X. Wang, M. Ottavi, F. Lombardi

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

6 Citations (Scopus)

Abstract

This paper presents a detailed analysis of the yield of embedded static random access memories (eSRAM) which are generated using a compiler. Defect and fault analysis inclusive of industrial data are presented for these chips by taking into account the design constructs (referred to as kernels) and the physical properties of the layout. The new tool CAYA (Compiler-based Array Yield Analysis) is based on a characterization of the design process which accounts for fault types and the relation between functional and structural faults; a novel empirical model is proposed to facilitate the yield calculation. Industrial data is provided for the analysis of various configurations with different structures and redundancy. The effectiveness and accuracy as provided by CAYA are assessed with respect to industrial designs.
Original languageEnglish
Title of host publicationProceedings 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Place of PublicationPiscataway, NJ
PublisherIEEE
Number of pages8
ISBN (Print)0-7695-2042-1
DOIs
Publication statusPublished - 2003
Externally publishedYes

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