Zapping thin film transistors

N. Golo-Tosic, F.G. Kuper, A.J. Mouthaan

Research output: Contribution to journalArticleAcademicpeer-review

3 Citations (Scopus)

Abstract

It was expected that hydrogenated amorphous silicon thin film transistors (alpha-Si:H TFTs) behave similarly to crystalline silicon transistors under electrostatic discharge (ESD) stress. It will be disproved in this paper. This knowledge is necessary in the design of the transistors used in a ESD protection circuit. The goal of this paper was to identify and to model failure under ESD zap. The drain of grounded gate TFTs has been stressed applying repeated square voltage pulses of different duration (100 ns to 10 s). The evolution and the mechanisms of the pre-breakdown degradation will be presented and discussed. Finally, the temperature distribution across an alpha-Si:H TFT under applied stress will be simulated by means of coupled electro-thermal simulations.
Original languageUndefined
Article number10.1016/S0026-2714(02)00041-0
Pages (from-to)747-765
Number of pages19
JournalMicroelectronics reliability
Volume42
Issue number4
DOIs
Publication statusPublished - 1 Apr 2002

Keywords

  • IR-67750
  • EWI-15575

Cite this

Golo-Tosic, N., Kuper, F. G., & Mouthaan, A. J. (2002). Zapping thin film transistors. Microelectronics reliability, 42(4), 747-765. [10.1016/S0026-2714(02)00041-0]. https://doi.org/10.1016/S0026-2714(02)00041-0
Golo-Tosic, N. ; Kuper, F.G. ; Mouthaan, A.J. / Zapping thin film transistors. In: Microelectronics reliability. 2002 ; Vol. 42, No. 4. pp. 747-765.
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Golo-Tosic, N, Kuper, FG & Mouthaan, AJ 2002, 'Zapping thin film transistors' Microelectronics reliability, vol. 42, no. 4, 10.1016/S0026-2714(02)00041-0, pp. 747-765. https://doi.org/10.1016/S0026-2714(02)00041-0

Zapping thin film transistors. / Golo-Tosic, N.; Kuper, F.G.; Mouthaan, A.J.

In: Microelectronics reliability, Vol. 42, No. 4, 10.1016/S0026-2714(02)00041-0, 01.04.2002, p. 747-765.

Research output: Contribution to journalArticleAcademicpeer-review

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T1 - Zapping thin film transistors

AU - Golo-Tosic, N.

AU - Kuper, F.G.

AU - Mouthaan, A.J.

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N2 - It was expected that hydrogenated amorphous silicon thin film transistors (alpha-Si:H TFTs) behave similarly to crystalline silicon transistors under electrostatic discharge (ESD) stress. It will be disproved in this paper. This knowledge is necessary in the design of the transistors used in a ESD protection circuit. The goal of this paper was to identify and to model failure under ESD zap. The drain of grounded gate TFTs has been stressed applying repeated square voltage pulses of different duration (100 ns to 10 s). The evolution and the mechanisms of the pre-breakdown degradation will be presented and discussed. Finally, the temperature distribution across an alpha-Si:H TFT under applied stress will be simulated by means of coupled electro-thermal simulations.

AB - It was expected that hydrogenated amorphous silicon thin film transistors (alpha-Si:H TFTs) behave similarly to crystalline silicon transistors under electrostatic discharge (ESD) stress. It will be disproved in this paper. This knowledge is necessary in the design of the transistors used in a ESD protection circuit. The goal of this paper was to identify and to model failure under ESD zap. The drain of grounded gate TFTs has been stressed applying repeated square voltage pulses of different duration (100 ns to 10 s). The evolution and the mechanisms of the pre-breakdown degradation will be presented and discussed. Finally, the temperature distribution across an alpha-Si:H TFT under applied stress will be simulated by means of coupled electro-thermal simulations.

KW - IR-67750

KW - EWI-15575

U2 - 10.1016/S0026-2714(02)00041-0

DO - 10.1016/S0026-2714(02)00041-0

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Golo-Tosic N, Kuper FG, Mouthaan AJ. Zapping thin film transistors. Microelectronics reliability. 2002 Apr 1;42(4):747-765. 10.1016/S0026-2714(02)00041-0. https://doi.org/10.1016/S0026-2714(02)00041-0