Zapping thin film transistors

It was expected that hydrogenated amorphous silicon thin film transistors (alpha-Si:H TFTs) behave similarly to crystalline silicon transistors under electrostatic discharge (ESD) stress. It will be disproved in this paper. This knowledge is necessary in the design of the transistors used in a ESD protection circuit. The goal of this paper was to identify and to model failure under ESD zap. The drain of grounded gate TFTs has been stressed applying repeated square voltage pulses of different duration (100 ns to 10 s). The evolution and the mechanisms of the pre-breakdown degradation will be presented and discussed. Finally, the temperature distribution across an alpha-Si:H TFT under applied stress will be simulated by means of coupled electro-thermal simulations.